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XR16V564D PDF预览

XR16V564D

更新时间: 2024-11-22 04:23:31
品牌 Logo 应用领域
艾科嘉 - EXAR 先进先出芯片
页数 文件大小 规格书
55页 1146K
描述
2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO

XR16V564D 数据手册

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XR16V564/564D  
2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO  
MAY 2007  
REV. 1.0.1  
FEATURES  
GENERAL DESCRIPTION  
Pin-to-pin compatible with ST16C454, ST16C554,  
TI’s TL16C754B and Philip’s SC16C754B  
1
The XR16V564 (V564) is an enhanced quad  
Universal Asynchronous Receiver and Transmitter  
(UART) with 32 bytes of transmit and receive FIFOs,  
programmable transmit and receive FIFO trigger  
levels, automatic hardware and software flow control,  
and data rates of up to 16 Mbps at 4X sampling rate.  
Each UART has a set of registers that provide the  
user with operating status and control, receiver error  
indications, and modem serial interface controls. An  
internal loopback capability allows onboard  
diagnostics. The V564 is available in a 48-pin QFN,  
64-pin LQFP, 68-pin PLCC and 80-pin LQFP  
packages. The 64-pin and 80-pin packages only offer  
the 16 mode interface, but the 48 and 68 pin  
packages offer an additional 68 mode interface which  
allows easy integration with Motorola processors.  
The XR16V564IV (64-pin) offers three state interrupt  
output while the XR16V564DIV provides continuous  
interrupt output. The XR16V564 is compatible with  
the industry standard ST16C554 and ST16C654/  
654D.  
Intel or Motorola Data Bus Interface select  
Four independent UART channels  
Register Set Compatible to 16C550  
Data rates of up to 16 Mbps  
32 byte Transmit FIFO  
32 byte Receive FIFO with error tags  
4 Selectable TX and RX FIFO Trigger Levels  
Automatic Hardware (RTS/CTS) Flow Control  
Automatic Software (Xon/Xoff) Flow Control  
Programmable Xon/Xoff characters  
Wireless Infrared (IrDA 1.0) Encoder/Decoder  
Full modem interface  
2.25V to 3.6V supply operation  
Sleep Mode with automatic wake-up  
Crystal oscillator or external clock input  
APPLICATIONS  
NOTE: 1 Covered by U.S. Patent #5,649,122.  
Portable Appliances  
Telecommunication Network Routers  
Ethernet Network Routers  
Cellular Data Devices  
Factory Automation and Process Controls  
FIGURE 1. XR16V564 BLOCK DIAGRAM  
2.25V to 3.6V VCC  
GND  
* 5 Volt Tolerant Inputs  
(Except XTAL1 input)  
A2:A0  
D7:D0  
IOR#  
UART Channel A  
32 Byte TX FIFO  
UART  
Regs  
TXA, RXA, DTRA#,  
DSRA#, RTSA#, CTSA#,  
CDA#, RIA#  
IOW#  
CSA#  
CSB#  
IR  
TX & RX  
ENDEC  
BRG  
32 Byte RX FIFO  
CSC#  
CSD#  
INTA  
INTB  
INTC  
TXB, RXB, DTRB#,  
DSRB#, RTSB#, CTSB#,  
CDB#, RIB#  
UART Channel B  
(same as Channel A)  
Data Bus  
Interface  
TXC, RXC, DTRC#,  
DSRC#, RTSC#, CTSC#,  
CDC#, RIC#  
UART Channel C  
(same as Channel A)  
INTD  
TXRDY# A-D  
RXRDY# A-D  
TXD, RXD, DTRD#,  
DSRD#, RTSD#, CTSD#,  
CDD#, RID#  
UART Channel D  
(same as Channel A)  
Reset  
16/68#  
INTSEL  
CLKSEL  
XTAL1  
XTAL2  
Crystal Osc/Buffer  
564 BLK  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com  

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