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XR16M654IL48-F PDF预览

XR16M654IL48-F

更新时间： 2024-11-22 13:16:11
品牌 Logo 应用领域
艾科嘉 - EXAR 微控制器和处理器串行IO控制器通信控制器外围集成电路先进先出芯片数据传输时钟
页数 文件大小 规格书
58页 1260K
描述
Serial I/O Controller, CMOS, PQCC48

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中文翻译

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XR16M654IL48-F 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：QCCN, LCC48,.27SQ,20Reach Compliance Code：compliant
风险等级：5.72JESD-30 代码：S-PQCC-N48
JESD-609代码：e3端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QCCN
封装等效代码：LCC48,.27SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER电源：1.8/3.3 V
认证状态：Not Qualified子类别：Serial IO/Communication Controllers
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUADuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches：1

XR16M654IL48-F 数据手册

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XR16M654/654D  
1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO  
MAY 2008  
REV. 1.0.0  
FEATURES  
GENERAL DESCRIPTION  
•
Pin-to-pin compatible with ST16C454, ST16C554,  
TI’s TL16C754B and NXP’s SC16C654B  
1
The XR16M654 (M654) is an enhanced quad  
Universal Asynchronous Receiver and Transmitter  
(UART) each with 64 bytes of transmit and receive  
FIFOs, programmable transmit and receive FIFO  
trigger levels, automatic hardware and software flow  
control, and data rates of up to 16 Mbps at 4X  
sampling rate. Each UART has a set of registers that  
provide the user with operating status and control,  
receiver error indications, and modem serial interface  
controls. An internal loopback capability allows  
onboard diagnostics. The M654 is available in a 48-  
pin QFN, 64-pin LQFP, 68-pin PLCC, 80-pin LQFP  
and 100-pin QFP packages. The 64-pin and 80-pin  
packages only offer the 16 mode interface, but the  
48, 68 and 100 pin packages offer an additional 68  
mode interface which allows easy integration with  
Motorola processors. The XR16M654IV (64-pin)  
offers three state interrupt output while the  
XR16M654DIV provides continuous interrupt output.  
The 100 pin package provides additional FIFO status  
outputs (TXRDY# and RXRDY# A-D), separate  
infrared transmit data outputs (IRTX A-D) and  
channel C external clock input (CHCCLK). The  
XR16M654 is compatible with the industry standard  
ST16C554 and ST16C654/654D.  
•
•
Intel or Motorola Data Bus Interface select  
Four independent UART channels  
■
■
■
■
■
■
■
■
■
■
Register Set Compatible to 16C550  
Data rates of up to 16 Mbps  
64 Byte Transmit FIFO  
64 Byte Receive FIFO with error tags  
4 Selectable TX and RX FIFO Trigger Levels  
Automatic Hardware (RTS/CTS) Flow Control  
Automatic Software (Xon/Xoff) Flow Control  
Progammable Xon/Xoff characters  
Wireless Infrared (IrDA 1.0) Encoder/Decoder  
Full modem interface  
•
•
•
1.62V to 3.63V supply operation  
Sleep Mode with automatic wake-up  
Crystal oscillator or external clock input  
APPLICATIONS  
•
•
•
•
•
Portable Appliances  
Telecommunication Network Routers  
Ethernet Network Routers  
NOTE: 1 Covered by U.S. Patent #5,649,122.  
Cellular Data Devices  
Factory Automation and Process Controls  
F
IGURE 1. XR16M654 BLOCK DIAGRAM  
1.62V to 3.6V VCC  
GND  
A2:A0  
D7:D0  
UART Channel A  
64 Byte TX FIFO  
IOR#  
IOW#  
CSA#  
CSB#  
UART  
Regs  
TXA, RXA, IRTXA, DTRA#,  
DSRA#, RTSA#, CTSA#,  
CDA#, RIA#  
IR  
TX & RX  
ENDEC  
BRG  
64 Byte RX FIFO  
CSC#  
CSD#  
TXB, RXB, IRTXB, DTRB#,  
DSRB#, RTSB#, CTSB#,  
CDB#, RIB#  
UART Channel B  
(same as Channel A)  
INTA  
INTB  
INTC  
Data Bus  
Interface  
TXC, RXC, IRTXC, DTRC#,  
DSRC#, RTSC#, CTSC#,  
CDC#, RIC#  
UART Channel C  
(same as Channel A)  
INTD  
CHCCLK  
TXRDY# A-D  
RXRDY# A-D  
TXD, RXD, IRTXD, DTRD#,  
DSRD#, RTSD#, CTSD#,  
CDD#, RID#  
UART Channel D  
(same as Channel A)  
Reset  
16/68#  
INTSEL  
XTAL1  
Crystal Osc/Buffer  
CLKSEL  
XTAL2  
654 BLK  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com  
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