Datasheet > XPC860DEZP50C1

XPC860DEZP50C1

更新时间： 2024-02-11 01:37:06

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟外围集成电路
页数	文件大小	规格书
64页	785K
描述
32-BIT, 50MHz, RISC PROCESSOR, PBGA357, PLASTIC, BGA-357

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XPC860DEZP50C1 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA,	针数：	357
Reach Compliance Code：	unknown	ECCN代码：	5A991
HTS代码：	8542.31.00.01	风险等级：	5.52
Is Samacsys：	N	地址总线宽度：	32
位大小：	32	最大时钟频率：	50 MHz
外部数据总线宽度：	32	JESD-30 代码：	S-PBGA-B357
长度：	25 mm	端子数量：	357
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	SQUARE	封装形式：	GRID ARRAY
认证状态：	Not Qualified	座面最大高度：	2.05 mm
速度：	50 MHz	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	宽度：	25 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR, RISC	Base Number Matches：	1

XPC860DEZP50C1 数据手册

1.1 Overview

The MPC860 PowerPCª Quad Integrated Communications Controller (PowerQUICCª) is a versatile

one-chip integrated microprocessor and peripheral combination designed for a variety of controller

applications. It particularly excels in both communications and networking systems. The PowerQUICC unit

is referred to as the MPC860 in this manual.

The MPC860 is a PowerPC architecture-based derivative of MotorolaÕs MC68360 Quad Integrated

Communications Controller (QUICC ), referred to here as the QUICC. The CPU on the MPC860 is a 32-

bit PowerPC implementation that incorporates memory management units (MMUs) and instruction and

data caches. The communications processor module (CPM) from the MC68360 QUICC has been enhanced

by the addition of the inter-integrated controller (I C) channel. Digital signal processing (DSP) functionality

has been added to the CPM. The memory controller has been enhanced, enabling the MPC860 to support

any type of memory, including high-performance memories and new types of DRAMs. A PCMCIA socket

controller supports up to two sockets. A real-time clock has also been integrated.

1.2 Features

The following list summarizes the key MPC860 features:

Embedded PowerPC core

Single-issue, 32-bit version of the core (compatible the PowerPC architecture deÞnition) with 32,

32-bit general-purpose registers (GPRs)

Ñ The core performs branch prediction with conditional prefetch, without conditional execution

Ñ 4-Kbyte data cache and 4-Kbyte instruction cache

Ñ Instruction and data caches are two-way, set-associative, physical address, least recently used

(LRU) replacement, lockable on-line granularity

Ñ MMUs with 32 entry TLB, fully associative instruction and data TLBs

Ñ MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address

spaces and 16 protection groups

Ñ Advanced on-chip-emulation debug mode

Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

32 address lines

Complete static design (0Ð40 MHz operation)

Memory controller (eight banks)

Ñ Contains complete dynamic RAM (DRAM) controller

Ñ Each bank can be a chip select or RAS to support a DRAM bank

Ñ Up to 15 wait states programmable per memory bank

Ñ Glueless interface to DRAM, SIMMS, SRAM, EPROM, ßash EPROM, and other memory

devices.

Ñ DRAM controller programmable to support most size and speed memory interfaces

Ñ Four CAS lines, four WE lines, one OE line

Ñ Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

Ñ Variable block sizes (32 KbyteÐ256 Mbyte)

MPC860 Hardware SpeciÞcations

MOTOROLA

123 4 5 6 7...64

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