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QPro Virtex-II 1.5V Radiation
Hardened QML Platform FPGAs
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DS124 (v1.1) January 8, 2004
Product Specification
Summary of Radiation Hardened QPro™ Virtex™-II Features
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Precise clock de-skew
Flexible frequency synthesis
High-resolution phase shifting
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Industry First Radiation Hardened Platform FPGA
Solution
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Guaranteed total ionizing dose to 200K Rad(si)
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16 global clock multiplexer buffers
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Latch-up immune to LET > 160 MeV-cm /mg
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Active Interconnect Technology
SEU in GEO upsets < 1.5E-6 per device day
achievable with recommended redundancy
implementation
Certified to MIL-PRF-38535 (Qualified Manufacturer
Listing)
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Fourth generation segmented routing structure
Predictable, fast routing delay, independent of
fanout
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SelectIO™-Ultra Technology
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Up to 824 user I/Os
Guaranteed over the full military temperature range
(–55°C to +125° C)
Ceramic and Plastic Wire-Bond and Flip-Chip Grid
Array Packages
IP-Immersion Architecture
19 single-ended and six differential standards
Programmable sink current (2 mA to 24 mA) per
I/O
Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
Differential Signaling
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Densities from 1M to 6M system gates
300+ MHz internal clock speed (Advance Data)
622+ Mb/s I/O (Advance Data)
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622 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
Bus LVDS I/O
Lightning Data Transport (LDT) I/O with current
driver buffers
Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
Built-in DDR input and output registers
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SelectRAM™ Memory Hierarchy
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2.5 Mb of dual-port RAM in 18 Kbit block
SelectRAM resources
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Up to 1 Mb of distributed SelectRAM resources
High-Performance Interfaces to External Memory
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DRAM interfaces
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Proprietary high-performance SelectLink
Technology
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SDR/DDR SDRAM
Network FCRAM
Reduced Latency DRAM
High-bandwidth data path
Double Data Rate (DDR) link
Web-based HDL generation methodology
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SRAM interfaces
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SDR/DDR SRAM
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Supported by Xilinx Foundation Series™ and Alliance
Series™ Development Systems
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QDR SRAM
CAM interfaces
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Integrated VHDL and Verilog design flows
Compilation of 10M system gates designs
Internet Team Design (ITD) tool
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Arithmetic Functions
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Dedicated 18-bit x 18-bit multiplier blocks
Fast look-ahead carry logic chains
SRAM-Based In-System Configuration
Flexible Logic Resources
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Fast SelectMAP configuration
IEEE 1532 support
Partial reconfiguration
Unlimited reprogrammability
Readback capability
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Up to 67,584 internal registers/latches with Clock
Enable
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Up to 67,584 look-up tables (LUTs) or cascadable
16-bit shift registers
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Wide multiplexers and wide-input function support
Horizontal cascade chain and sum-of-products
support
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0.15 µm 8-Layer Metal Process with 0.12 µm
High-Speed Transistors
1.5V (VCCINT) Core Power Supply, Dedicated 3.3V
VCCAUX Auxiliary and VCCO I/O Power Supplies
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Internal 3-state busing
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High-Performance Clock Management Circuitry
Up to 12 DCM (Digital Clock Manager) modules
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IEEE 1149.1 Compatible Boundary-Scan Logic Support
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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS124 (v1.1) January 8, 2004
www.xilinx.com
1
Product Specification
1-800-255-7778