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XDPE1A2G7B-0000 PDF预览

XDPE1A2G7B-0000

更新时间: 2024-10-15 17:15:51
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
7页 578K
描述
XDPE1A2G7B digital dual loop 16 phase controller provides power for nVIDIA AI servers, workstation

XDPE1A2G7B-0000 数据手册

 浏览型号XDPE1A2G7B-0000的Datasheet PDF文件第2页浏览型号XDPE1A2G7B-0000的Datasheet PDF文件第3页浏览型号XDPE1A2G7B-0000的Datasheet PDF文件第4页浏览型号XDPE1A2G7B-0000的Datasheet PDF文件第5页浏览型号XDPE1A2G7B-0000的Datasheet PDF文件第6页浏览型号XDPE1A2G7B-0000的Datasheet PDF文件第7页 
XDPE1A2G7B  
XDPE1A2G7B Digital Multi-phase Controller  
16-phase Dual Loop Voltage Regulator  
Features  
Digital controller assisted with high performance analog front ends with a fully programmable ARM®  
CortexTM M0 Processor  
Compliant with nVIDIA custom PWMVID specification  
Compliant with PMBus rev 1.3.1 (March 2015) serial interface  
Query voltage, current, temperature faults  
Fault Response  
Maximum supported bus speed 1 MHz  
Support 1.8/3.3 V operation  
Output voltage regulation range  
0.05 V to 2.75 V (5 mV/step)  
Digitally controlled phasing for full flexibility in both loop configuration and phase firing order  
Configurable autonomous phase add/drop  
Automatic phase detection at start-up  
Supports start-up into pre-bias voltage  
Integrated power stage current sense  
Differential output voltage sense  
Fast current balancing with current-mode control  
Digitally programmable PID (Proportional, Integral, Differential) loop compensation  
Digitally programmable load line slope and offset  
Digital temperature compensation  
Direct input (+12 V) voltage and current sense  
Extensive fault detection and protection capability  
IUVP, OUVP & OOVP (fixed and tracking)  
OCP instantaneous & averaged (total current)  
Multiple OTP thresholds  
Peak phase current pulse limiting  
Negative current limit protection  
Internal non-volatile memory (NVM) to store multiple custom configurations  
RoHS compliant and Halogen free 56-lead QFN plastic package  
Final Datasheet  
www.infineon.com  
Please read the Important Notice and Warnings at the end of this document  
1 of 6  
Rev 2.1  
2024-03-27  
 

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