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XCV1000-4BGG560I

更新时间： 2024-02-04 01:30:07
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
76页 530K
描述
Field Programmable Gate Array, 6144 CLBs, 1124022 Gates, 250MHz, CMOS, PBGA560, BGA-560

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XCV1000-4BGG560I 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA,针数：560
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.8最大时钟频率：250 MHz
CLB-Max的组合延迟：0.8 nsJESD-30 代码：S-PBGA-B560
JESD-609代码：e1长度：42.5 mm
湿度敏感等级：3可配置逻辑块数量：6144
等效关口数量：1124022端子数量：560
组织：6144 CLBS, 1124022 GATES封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE峰值回流温度（摄氏度）：260
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：1.7 mm最大供电电压：2.625 V
最小供电电压：2.375 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
端子面层：Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：42.5 mm
Base Number Matches：1

XCV1000-4BGG560I 数据手册

 浏览型号XCV1000-4BGG560I的Datasheet PDF文件第2页浏览型号XCV1000-4BGG560I的Datasheet PDF文件第3页浏览型号XCV1000-4BGG560I的Datasheet PDF文件第4页浏览型号XCV1000-4BGG560I的Datasheet PDF文件第5页浏览型号XCV1000-4BGG560I的Datasheet PDF文件第6页浏览型号XCV1000-4BGG560I的Datasheet PDF文件第7页 
0
R
Virtex™ 2.5 V  
Field Programmable Gate Arrays  
0
0
DS003-1 (v2.5 ) April 2, 2001  
Product Specification  
Features  
•
Fast, high-density Field-Programmable Gate Arrays  
•
•
Supported by FPGA Foundation™ and Alliance  
Development Systems  
-
-
-
-
Densities from 50k to 1M system gates  
System performance up to 200 MHz  
66-MHz PCI Compliant  
-
Complete support for Unified Libraries, Relationally  
Placed Macros, and Design Manager  
-
Wide selection of PC and workstation platforms  
Hot-swappable for Compact PCI  
SRAM-based in-system configuration  
•
•
Multi-standard SelectIO™ interfaces  
-
-
Unlimited re-programmability  
Four programming modes  
-
-
16 high-performance interface standards  
Connects directly to ZBTRAM devices  
•
•
0.22 µm 5-layer metal process  
100% factory tested  
Built-in clock-management circuitry  
-
Four dedicated delay-locked loops (DLLs) for  
advanced clock control  
Description  
-
Four primary low-skew global clock distribution  
nets, plus 24 secondary local clock nets  
The Virtex FPGA family delivers high-performance,  
high-capacity programmable logic solutions. Dramatic  
increases in silicon efficiency result from optimizing the new  
architecture for place-and-route efficiency and exploiting an  
aggressive 5-layer-metal 0.22 µm CMOS process. These  
advances make Virtex FPGAs powerful and flexible alterna-  
tives to mask-programmed gate arrays. The Virtex family  
comprises the nine members shown in Table 1.  
•
•
Hierarchical memory system  
-
-
-
LUTs configurable as 16-bit RAM, 32-bit RAM,  
16-bit dual-ported RAM, or 16-bit Shift Register  
Configurable synchronous dual-ported 4k-bit  
RAMs  
Fast interfaces to external high-performance RAMs  
Flexible architecture that balances speed and density  
-
-
-
-
Dedicated carry logic for high-speed arithmetic  
Dedicated multiplier support  
Cascade chain for wide-input functions  
Abundant registers/latches with clock enable, and  
dual synchronous/asynchronous set and reset  
Internal 3-state bussing  
Building on experience gained from previous generations of  
FPGAs, the Virtex family represents a revolutionary step  
forward in programmable logic design. Combining a wide  
variety of programmable system features, a rich hierarchy of  
fast, flexible interconnect resources, and advanced process  
technology, the Virtex family delivers a high-speed and  
high-capacity programmable logic solution that enhances  
design flexibility while reducing time-to-market.  
-
-
-
IEEE 1149.1 boundary-scan logic  
Die-temperature sensor diode  
Table 1: Virtex Field-Programmable Gate Array Family Members  
Maximum  
Block RAM  
Bits  
Maximum  
SelectRAM+™ Bits  
Device  
System Gates  
CLB Array  
Logic Cells  
Available I/O  
XCV50  
57,906  
16x24  
1,728  
180  
180  
260  
284  
316  
404  
512  
512  
512  
32,768  
40,960  
49,152  
57,344  
65,536  
81,920  
98,304  
114,688  
131,072  
24,576  
38,400  
55,296  
75,264  
98,304  
153,600  
221,184  
301,056  
393,216  
XCV100  
XCV150  
XCV200  
XCV300  
XCV400  
XCV600  
XCV800  
XCV1000  
108,904  
20x30  
2,700  
164,674  
24x36  
3,888  
236,666  
28x42  
5,292  
322,970  
32x48  
6,912  
468,252  
40x60  
10,800  
15,552  
21,168  
27,648  
661,111  
48x72  
888,439  
56x84  
1,124,022  
64x96  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS003-1 (v2.5 ) April 2, 2001  
Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 1 of 4  
1
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XCV1000-5BG560C XILINX Field Programmable Gate Arrays

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XCV1000-5BG560I XILINX Field Programmable Gate Arrays

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XCV1000-5BGG560C XILINX Field Programmable Gate Array, 6144 CLBs, 1124022 Gates, 294MHz, CMOS, PBGA560, BGA-560

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XCV1000-5BGG560I XILINX Field Programmable Gate Array, 6144 CLBs, 1124022 Gates, 294MHz, CMOS, PBGA560, BGA-560

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