Datasheet > XCS05XL-4VQG100C

XCS05XL-4VQG100C

更新时间： 2024-01-01 11:30:46

品牌	Logo	应用领域
赛灵思 - XILINX		时钟栅可编程逻辑
页数	文件大小	规格书
83页	770K
描述
Field Programmable Gate Array, 100 CLBs, 2000 Gates, 217MHz, 238-Cell, CMOS, PQFP100, PLASTIC, VQFP-100

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XCS05XL-4VQG100C 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	TFQFP, TQFP100,.63SQ
针数：	100	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.78	其他特性：	MAXIMUM USABLE GATES 5000
最大时钟频率：	217 MHz	CLB-Max的组合延迟：	1.1 ns
JESD-30 代码：	S-PQFP-G100	JESD-609代码：	e3
长度：	14 mm	湿度敏感等级：	3
可配置逻辑块数量：	100	等效关口数量：	2000
输入次数：	77	逻辑单元数量：	238
输出次数：	77	端子数量：	100
最高工作温度：	85 °C	最低工作温度：
组织：	100 CLBS, 2000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP	封装等效代码：	TQFP100,.63SQ
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	电源：	3.3 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm
Base Number Matches：	1

XCS05XL-4VQG100C 数据手册

Spartan and Spartan-XL FPGA Families Data Sheet

Clock Input

Table 2: CLB Storage Element Functionality

Each flip-flop can be triggered on either the rising or falling

clock edge. The CLB clock line is shared by both flip-flops.

However, the clock is individually invertible for each flip-flop

(see CK path in Figure 3). Any inverter placed on the clock

line in the design is automatically absorbed into the CLB.

Mode

Power-Up or

GSR

Flip-Flop

Operation

Clock Enable

The clock enable line (EC) is active High. The EC line is

shared by both flip-flops in a CLB. If either one is left discon-

nected, the clock enable for that flip-flop defaults to the

active state. EC is not invertible within the CLB. The clock

enable is synchronous to the clock and must satisfy the

setup and hold timing specified for the device.

Latch

Operation

(Spartan-XL)

Both

Legend:

Set/Reset

The set/reset line (SR) is an asynchronous active High con-

trol of the flip-flop. SR can be configured as either set or

reset at each flip-flop. This configuration option determines

the state in which each flip-flop becomes operational after

configuration. It also determines the effect of a GSR pulse

during normal operation, and the effect of a pulse on the SR

line of the CLB. The SR line is shared by both flip-flops. If

SR is not specified for a flip-flop the set/reset for that flip-flop

defaults to the inactive state. SR is not invertible within the

CLB.

Don’t care

Rising edge (clock not inverted).

Set or Reset value. Reset is default.

Input is Low or unconnected (default

value)

Input is High or unconnected (default

value)

CLB Signal Flow Control

In addition to the H-LUT input control multiplexers (shown in

box "A" of Figure 2, page 4) there are signal flow control

multiplexers (shown in box "B" of Figure 2) which select the

signals which drive the flip-flop inputs and the combinatorial

CLB outputs (X and Y).

GND

GSR

Each flip-flop input is driven from a 4:1 multiplexer which

selects among the three LUT outputs and DIN as the data

source.

Each combinatorial output is driven from a 2:1 multiplexer

which selects between two of the LUT outputs. The X output

can be driven from the F-LUT or H-LUT, the Y output from

G-LUT or H-LUT.

Control Signals

Vcc

There are four signal control multiplexers on the input of the

CLB. These multiplexers allow the internal CLB control sig-

nals (H1, DIN, SR, and EC in Figure 2 and Figure 4) to be

driven from any of the four general control inputs (C1-C4 in

Figure 4) into the CLB. Any of these inputs can drive any of

the four internal control signals.

Multiplexer Controlled

by Configuration Program

DS060_03_041901

Figure 3: CLB Flip-Flop Functional Block Diagram

DS060 (v1.8) June 26, 2008

www.xilinx.com

Product Specification

1 2 3 456 7 8...83

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与XCS05XL-4VQG100C相关器件

型号	品牌	描述	获取价格	数据表
XCS05XL-4VQG100Q	XILINX	Field Programmable Gate Array, 100 CLBs, 2000 Gates, 217MHz, CMOS, PQFP100, PLASTIC, VQFP-	获取价格
XCS05XL-5BG100C	XILINX	Spartan and Spartan-XL Families Field Programmable Gate Arrays	获取价格
XCS05XL-5BG100I	XILINX	Spartan and Spartan-XL Families Field Programmable Gate Arrays	获取价格
XCS05XL-5BG144C	XILINX	Spartan and Spartan-XL Families Field Programmable Gate Arrays	获取价格
XCS05XL-5BG144I	XILINX	Spartan and Spartan-XL Families Field Programmable Gate Arrays	获取价格
XCS05XL-5BG208C	XILINX	Spartan and Spartan-XL Families Field Programmable Gate Arrays	获取价格

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