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XCS05XL-4VQG100Q PDF预览

XCS05XL-4VQG100Q

更新时间： 2024-02-18 21:38:02
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
4页 54K
描述
Field Programmable Gate Array, 100 CLBs, 2000 Gates, 217MHz, CMOS, PQFP100, PLASTIC, VQFP-100

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XCS05XL-4VQG100Q 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TFQFP,针数：100
Reach Compliance Code：compliant风险等级：5.81
其他特性：MAXIMUM USABLE GATES = 5000最大时钟频率：217 MHz
CLB-Max的组合延迟：1.1 nsJESD-30 代码：S-PQFP-G100
JESD-609代码：e3长度：14 mm
湿度敏感等级：3可配置逻辑块数量：100
等效关口数量：2000端子数量：100
最高工作温度：125 °C最低工作温度：-40 °C
组织：100 CLBS, 2000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

XCS05XL-4VQG100Q 数据手册

 浏览型号XCS05XL-4VQG100Q的Datasheet PDF文件第2页浏览型号XCS05XL-4VQG100Q的Datasheet PDF文件第3页浏览型号XCS05XL-4VQG100Q的Datasheet PDF文件第4页 
0
Spartan-XL 3.3V FPGA  
Automotive IQ Family:  
Introduction and Ordering  
Product Specification  
R
0
0
DS107-1 (v1.4) October 18, 2004  
Introduction  
The Spartan™-XL 3.3V FPGA Automotive IQ product family  
is a high-volume production FPGA solution that delivers all  
the key requirements for ASIC replacement up to 40,000  
gates. These requirements include high-performance,  
on-chip RAM, core solutions, and prices that, in high vol-  
ume, approach and in many cases, are equivalent to mask  
programmed ASIC devices. By streamlining the Spartan-XL  
series feature set, leveraging process technology and  
focusing on total cost management, the Spartan-XL series  
delivers the key features required by ASIC and other  
high-volume logic users while avoiding the initial cost, long  
development cycles, and inherent risk of conventional  
ASICs.  
•
System level features  
-
-
On-chip SelectRAM™ memory  
Full readback capability for program verification  
and internal node observability  
-
-
-
-
-
Dedicated high-speed carry logic  
Internal 3-state bus capability  
Eight global low-skew clock or signal networks  
IEEE 1149.1-compatible Boundary Scan logic  
Footprint compatibility in common packages  
•
Fully supported by powerful Xilinx development system  
-
ISE Foundation™ Series: Integrated, shrink-wrap  
software  
-
ISE Alliance Series™: Dozens of PC and  
workstation third party development systems  
supported  
Features  
•
Guaranteed to meet full electrical specifications over  
-
Fully automatic mapping, placement and routing  
TJ = –40°C to +125°C  
•
•
•
•
•
•
•
•
•
•
•
•
3.3V supply for low power with 5V tolerant I/Os  
Power down input  
•
ASIC replacement FPGA for high-volume production  
with on-chip RAM  
Higher performance  
•
•
•
Density up to 1,862 logic cells or 40,000 system gates  
Streamlined feature set based on XC4000 architecture  
Faster carry logic  
More flexible high-speed clock network  
Latch capability in Configurable Logic Blocks  
Input fast capture latch  
Optional mux or 2-input function generator on outputs  
12 mA or 24 mA output drive  
Enhanced Boundary Scan  
Broad set of AllianceCORE™ and LogiCORE™  
predefined solutions available  
•
Unlimited reprogrammability  
Express Mode configuration  
Refer to Spartan-XL and Spartan FPGAs complete  
data sheet (DS060) for product description, AC and DC  
specifications  
Table 1: Spartan-XL Field Programmable Gate Arrays  
Typical  
Max.  
Avail. Distributed  
CLBs Flip-flops User I/O RAM Bits  
Total  
Logic  
Max System  
Gates  
Gate Range  
CLB  
Total  
No. of  
Device  
Cells  
238  
(Logic and RAM)(1) Matrix  
XCS05XL  
XCS10XL  
XCS20XL  
XCS30XL  
XCS40XL  
5,000  
10,000  
20,000  
30,000  
40,000  
2,000-5,000  
3,000-10,000  
7,000-20,000  
10,000-30,000  
13,000-40,000  
10 x 10  
14 x 14  
20 x 20  
24 x 24  
28 x 28  
100  
196  
400  
576  
784  
360  
616  
77  
3,200  
6,272  
466  
112  
160  
192  
224  
950  
1,120  
1,536  
2,016  
12,800  
18,432  
25,088  
1,368  
1,862  
Notes:  
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.  
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS107-1 (v1.4) October 18, 2004  
www.xilinx.com  
1
Product Specification  
1-800-255-7778  
1234

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