Datasheet > XCS05XL-4VQG100C

XCS05XL-4VQG100C

更新时间： 2024-01-31 22:32:32

品牌	Logo	应用领域
赛灵思 - XILINX		时钟栅可编程逻辑
页数	文件大小	规格书
83页	770K
描述
Field Programmable Gate Array, 100 CLBs, 2000 Gates, 217MHz, 238-Cell, CMOS, PQFP100, PLASTIC, VQFP-100

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XCS05XL-4VQG100C 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	TFQFP, TQFP100,.63SQ
针数：	100	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.78	其他特性：	MAXIMUM USABLE GATES 5000
最大时钟频率：	217 MHz	CLB-Max的组合延迟：	1.1 ns
JESD-30 代码：	S-PQFP-G100	JESD-609代码：	e3
长度：	14 mm	湿度敏感等级：	3
可配置逻辑块数量：	100	等效关口数量：	2000
输入次数：	77	逻辑单元数量：	238
输出次数：	77	端子数量：	100
最高工作温度：	85 °C	最低工作温度：
组织：	100 CLBS, 2000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP	封装等效代码：	TQFP100,.63SQ
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	电源：	3.3 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm
Base Number Matches：	1

XCS05XL-4VQG100C 数据手册

Spartan and Spartan-XL FPGA Families Data Sheet

G-LUT

Logic

Function

G1-G4

H-LUT

Logic

Function

F-G-H1

DIN

Logic

Function

F1-F4

F-LUT

Multiplexer Controlled

by Configuration Program

DS060_02_0506 01

Figure 2: Spartan/XL Simplified CLB Logic Diagram (some features not shown)

A CLB can implement any of the following functions:

Flip-Flops

•

Any function of up to four variables, plus any second

function of up to four unrelated variables, plus any third

function of up to three unrelated variables

Each CLB contains two flip-flops that can be used to regis-

ter (store) the function generator outputs. The flip-flops and

function generators can also be used independently (see

Figure 2). The CLB input DIN can be used as a direct input

to either of the two flip-flops. H1 can also drive either

flip-flop via the H-LUT with a slight additional delay.

Note: When three separate functions are generated, one of

the function outputs must be captured in a flip-flop internal to

the CLB. Only two unregistered function generator outputs

are available from the CLB.

The two flip-flops have common clock (CK), clock enable

(EC) and set/reset (SR) inputs. Internally both flip-flops are

also controlled by a global initialization signal (GSR) which

is described in detail in Global Signals: GSR and GTS,

page 20.

•

Any single function of five variables

Any function of four variables together with some

functions of six variables

•

Some functions of up to nine variables.

Implementing wide functions in a single block reduces both

the number of blocks required and the delay in the signal

path, achieving both increased capacity and speed.

Latches (Spartan-XL Family Only)

The Spartan-XL family CLB storage elements can also be

configured as latches. The two latches have common clock

(K) and clock enable (EC) inputs. Functionality of the stor-

age element is described in Table 2.

The versatility of the CLB function generators significantly

improves system speed. In addition, the design-software

tools can deal with each function generator independently.

This flexibility improves cell usage.

www.xilinx.com

DS060 (v1.8) June 26, 2008

Product Specification

1 2 345 6 7...83

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与XCS05XL-4VQG100C相关器件

型号	品牌	描述	获取价格	数据表
XCS05XL-4VQG100Q	XILINX	Field Programmable Gate Array, 100 CLBs, 2000 Gates, 217MHz, CMOS, PQFP100, PLASTIC, VQFP-	获取价格
XCS05XL-5BG100C	XILINX	Spartan and Spartan-XL Families Field Programmable Gate Arrays	获取价格
XCS05XL-5BG100I	XILINX	Spartan and Spartan-XL Families Field Programmable Gate Arrays	获取价格
XCS05XL-5BG144C	XILINX	Spartan and Spartan-XL Families Field Programmable Gate Arrays	获取价格
XCS05XL-5BG144I	XILINX	Spartan and Spartan-XL Families Field Programmable Gate Arrays	获取价格
XCS05XL-5BG208C	XILINX	Spartan and Spartan-XL Families Field Programmable Gate Arrays	获取价格

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