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XCR3064A-7VQ100C

更新时间： 2024-11-11 03:09:55

品牌	Logo	应用领域
赛灵思 - XILINX		可编程逻辑器件输入元件时钟
页数	文件大小	规格书
18页	550K
描述
64 Macrocell CPLD With Enhanced Clocking

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XCR3064A-7VQ100C 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	TFQFP, TQFP100,.63SQ
针数：	100	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.65
Is Samacsys：	N	其他特性：	YES
最大时钟频率：	111 MHz	系统内可编程：	YES
JESD-30 代码：	S-PQFP-G100	JTAG BST：	YES
长度：	14 mm	湿度敏感等级：	3
专用输入次数：	2	I/O 线路数量：	64
宏单元数：	64	端子数量：	100
最高工作温度：	70 °C	最低工作温度：
组织：	2 DEDICATED INPUTS, 64 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFQFP
封装等效代码：	TQFP100,.63SQ	封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE, FINE PITCH	电源：	3.3 V
可编程逻辑类型：	EE PLD	传播延迟：	7.5 ns
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	Programmable Logic Devices	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

XCR3064A-7VQ100C 数据手册

APPLICATION NOTE

XCR3064A: 64 Macrocell CPLD With

Enhanced Clocking

14*

DS037 (v1.1) February 10, 2000

Product Specification

Features

Description

•

Industry's first TotalCMOS™ PLD - both CMOS design

and process technologies

Fast Zero Power (FZP™) design technique provides

ultra-low power and very high speed

3V, In-System Programmable (ISP) using a JTAG

interface

The XCR3064A CPLD (Complex Programmable Logic

Device) is the second in a family of CoolRunner™ CPLDs

from Xilinx. These devices combine high speed and zero

power in a 64 macrocell CPLD. With the FZP design tech-

nique, the XCR3064A offers true pin-to-pin speeds of 7.5

ns, while simultaneously delivering power that is less than

100 µA at standby without the need for "turbo bits" or other

power down schemes. By replacing conventional sense

amplifier methods for implementing product terms (a tech-

nique that has been used in PLDs since the bipolar era)

with a cascaded chain of pure CMOS gates, the dynamic

power is also substantially lower than any competing

CPLD. These devices are the first TotalCMOS PLDs, as

they use both a CMOS process technology and the pat-

ented full CMOS FZP design technique.

On-chip superVoltage generation

ISP commands include: Enable, Erase, Program,

Verify

Supported by multiple ISP programming platforms

Four pin JTAG interface (TCK, TMS, TDI, TDO)

JTAG commands include: Bypass, Idcode

•

High speed pin-to-pin delays of 7.5 ns

Ultra-low static power of less than 100 µA

5V tolerant I/Os to support mixed Voltage systems

100% routable with 100% utilization while all pins and

all macrocells are fixed

Deterministic timing model that is extremely simple to

use

Up to 12 clocks with programmable polarity at every

macrocell

Support for complex asynchronous clocking

Innovative XPLA™ architecture combines high speed

with extreme flexibility

1000 erase/program cycles guaranteed

20 years data retention guaranteed

Logic expandable to 37 product terms

The Xilinx FZP CPLDs utilize the patented XPLA

(eXtended Programmable Logic Array) architecture. The

XPLA architecture combines the best features of both PLA

and PAL type structures to deliver high speed and flexible

logic allocation that results in superior ability to make

design changes with fixed pinouts. The XPLA structure in

each logic block provides a fast 7.5 ns PAL path with five

dedicated product terms per output. This PAL path is joined

by an additional PLA structure that deploys a pool of 32

product terms to a fully programmable OR array that can

allocate the PLA product terms to any output in the logic

block. This combination allows logic to be allocated effi-

ciently throughout the logic block and supports as many as

37 product terms on an output. The speed with which logic

is allocated from the PLA array to an output is only 1.5 ns,

regardless of the number of PLA product terms used, which

•

Advanced 0.35µ E CMOS process

Security bit prevents unauthorized access

Design entry and verification using industry standard

and Xilinx CAE tools

•

Reprogrammable using industry standard device

programmers

Innovative Control Term structure provides either sum

terms or product terms in each logic block for:

results in worst case t 's of only 9.0 ns from any pin to any

other pin. In addition, logic that is common to multiple out-

puts can be placed on a single PLA product term and

shared across multiple outputs via the OR array, effectively

increasing design density.

Programmable 3-state buffer

Asynchronous macrocell register preset/reset

Up to two asynchronous clocks

The XCR3064A CPLDs are supported by industry standard

CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Syn-

opsys, Synario, Viewlogic, and Synplicity), using text

(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-

ification uses industry standard simulators for functional

and timing simulation. Development is supported on per-

sonal computer, Sparc, and HP platforms. Device fitting

uses a Xilinx developed tool, XPLA Professional (available

on the Xilinx web site).

•

Programmable global 3-state pin facilitates `bed of

nails' testing without using logic resources

Available in PLCC, VQFP, and Chip Scale BGA

packages

Industrial grade operates from 2.7V to 3.6V

DS037 (v1.1) February 10, 2000

www.xilinx.com

1-800-255-7778

12 3 4 5 6 7...18

中文翻译

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与XCR3064A-7VQ100C相关器件

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