Datasheet > XC7K160T-1FB484C

XC7K160T-1FB484C

更新时间： 2024-02-12 18:06:53

品牌	Logo	应用领域
赛灵思 - XILINX		时钟栅可编程逻辑
页数	文件大小	规格书
62页	696K
描述
Field Programmable Gate Array, 1818MHz, 162240-Cell, CMOS, PBGA484,

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XC7K160T-1FB484C 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	BGA, BGA484,22X22,40	Reach Compliance Code：	not_compliant
风险等级：	5.87	最大时钟频率：	1818 MHz
JESD-30 代码：	S-PBGA-B484	JESD-609代码：	e0
输入次数：	285	逻辑单元数量：	162240
输出次数：	285	端子数量：	484
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA484,22X22,40	封装形状：	SQUARE
封装形式：	GRID ARRAY	电源：	1,1.8,3.3 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
子类别：	Field Programmable Gate Arrays	表面贴装：	YES
技术：	CMOS	端子面层：	Tin/Lead (Sn63Pb37)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	Base Number Matches：	1

XC7K160T-1FB484C 数据手册

浏览型号XC7K160T-1FB484C的Datasheet PDF文件第10页

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

•

When V

is powered before V

current draw can increase by 460 mA per transceiver during V

and V

– V

> 150 mV and V

< 0.7V, the

MGTAVTT

MGTAVCC

MGTAVTT

MGTAVCC

ramp up. The duration of the current

MGTAVTT

MGTAVCC

draw can be up to 0.3 x T

(ramp time from GND to 90ꢀ of V

). The reverse is true for power-down.

MGTAVCC

When V

is powered before V

and V

– V

> 150 mV and V

< 0.7V, the V

current

MGTAVTT

CCINT

MGTAVTT

CCINT

draw can increase by 50 mA per transceiver during V

ramp up. The duration of the current draw can be up to

CCINT

0.3 x T

(ramp time from GND to 90ꢀ of V

). The reverse is true for power-down.

VCCINT

CCINT

Table 7 shows the minimum current, in addition to I

, that are required by Kintex-7 devices for proper power-on and

CCQ

configuration. If the current minimums shown in Table 6 and Table 7 are met, the device powers on after all five supplies have

passed through their power-on reset threshold voltages. The FPGA must not be configured until after V is applied.

CCINT

Once initialized and configured, use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power)

to estimate current drain on these supplies.

Table 7: Power-On Current for Kintex-7 Devices

Device

XC7K70T

I_CCINTMIN

I_CCAUXMIN

I_CCOMIN

I_{CCAUX_IOMIN}

I_CCBRAMMIN

Units

I_CCINTQ+ 450

I_CCINTQ+ 550

I_CCAUXQ+ 40 I_CCOQ+ 40 mA per bank I_CCOAUXIOQ+ 40 mA per bank I_CCBRAMQ+ 40

I_CCAUXQ+ 50 I_CCOQ+ 40 mA per bank I_CCOAUXIOQ+ 40 mA per bank I_CCBRAMQ+ 40

I_CCAUXQ+ 80 I_CCOQ+ 40 mA per bank I_CCOAUXIOQ+ 40 mA per bank I_CCBRAMQ+ 40

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

XQ7K325T

XQ7K410T

_CCINTQ+ 600

_CCINTQ+ 1450 I_CCAUXQ+ 109 I_CCOQ+ 40 mA per bank I_CCOAUXIOQ+ 40 mA per bank I_CCBRAMQ+ 81

I_CCINTQ+ 1500 I_CCAUXQ+ 125 I_CCOQ+ 40 mA per bank I_CCOAUXIOQ+ 40 mA per bank I_CCBRAMQ+ 90

_CCINTQ+ 2200 I_CCAUXQ+ 180 I_CCOQ+ 40 mA per bank I_CCOAUXIOQ+ 40 mA per bank I_CCBRAMQ+ 108

I_CCINTQ+ 600

I_CCAUXQ+ 80 I_CCOQ+ 40 mA per bank I_CCOAUXIOQ+ 40 mA per bank I_CCBRAMQ+ 40

_CCINTQ+ 1500 I_CCAUXQ+ 125 I_CCOQ+ 40 mA per bank I_CCOAUXIOQ+ 40 mA per bank I_CCBRAMQ+ 90

Table 8: Power Supply Ramp Time

Symbol

Description

Conditions

Min

0.2

–

Max

Units

T_VCCINT

Ramp time from GND to 90ꢀ of V_CCINT

Ramp time from GND to 90ꢀ of V_CCO

Ramp time from GND to 90ꢀ of V_CCAUX

Ramp time from GND to 90ꢀ of V_{CCAUX_IO}

Ramp time from GND to 90ꢀ of V_CCBRAM

T_VCCO

T_VCCAUX

T_{VCCAUX_IO}

T_VCCBRAM

T_J= 125°C⁽¹⁾

T_J= 100°C⁽¹⁾

T_J= 85°C⁽¹⁾

300

500

800

T_VCCO2VCCAUX

Allowed time per power cycle for V_CCO– V_CCAUX> 2.625V

–

T_MGTAVCC

T_MGTAVTT

Ramp time from GND to 90ꢀ of V_MGTAVCC

Ramp time from GND to 90ꢀ of V_MGTAVTT

Ramp time from GND to 90ꢀ of V_MGTVCCAUX

0.2

T_MGTVCCAUX

Notes:

1. Based on 240,000 power cycles with nominal V

of 3.3V or 36,500 power cycles with a worst case V

of 3.465V.

CCO

DS182 (v2.8) March 4, 2014

Product Specification

www.xilinx.com

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