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XC7K160T-1FB484C

更新时间： 2024-02-03 10:46:15
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
62页 696K
描述
Field Programmable Gate Array, 1818MHz, 162240-Cell, CMOS, PBGA484,

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XC7K160T-1FB484C 技术参数

是否Rohs认证： 不符合生命周期：Active
包装说明：BGA, BGA484,22X22,40Reach Compliance Code：not_compliant
风险等级：5.87最大时钟频率：1818 MHz
JESD-30 代码：S-PBGA-B484JESD-609代码：e0
输入次数：285逻辑单元数量：162240
输出次数：285端子数量：484
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA484,22X22,40封装形状：SQUARE
封装形式：GRID ARRAY电源：1,1.8,3.3 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
子类别：Field Programmable Gate Arrays表面贴装：YES
技术：CMOS端子面层：Tin/Lead (Sn63Pb37)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOMBase Number Matches：1

XC7K160T-1FB484C 数据手册

 浏览型号XC7K160T-1FB484C的Datasheet PDF文件第1页浏览型号XC7K160T-1FB484C的Datasheet PDF文件第2页浏览型号XC7K160T-1FB484C的Datasheet PDF文件第3页浏览型号XC7K160T-1FB484C的Datasheet PDF文件第5页浏览型号XC7K160T-1FB484C的Datasheet PDF文件第6页浏览型号XC7K160T-1FB484C的Datasheet PDF文件第7页 
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics  
Table 3: DC Characteristics Over Recommended Operating Conditions (Cont’d)  
Symbol  
Description  
Pad pull-down (when selected) @ VIN = 3.3V  
Pad pull-down (when selected) @ VIN = 1.8V  
Analog supply current, analog circuits in powered up state  
Battery supply current  
Min  
68  
45  
–
Typ(1)  
Max  
330  
180  
25  
Units  
µA  
–
–
IRPD  
µA  
ICCADC  
–
mA  
nA  
(3)  
IBATT  
–
–
150  
55  
Thevenin equivalent resistance of programmable input termination to VCCO/2  
(UNTUNED_SPLIT_40)  
28  
40  
Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2  
(UNTUNED_SPLIT_50)  
35  
44  
50  
60  
65  
83  
Ω
Ω
(4)  
RIN_TERM  
Thevenin equivalent resistance of programmable input termination to VCCO/2  
(UNTUNED_SPLIT_60)  
n
r
Temperature diode ideality factor  
–
–
1.010  
2
–
–
–
Temperature diode series resistance  
Ω
Notes:  
1. Typical values are specified at nominal voltage, 25°C.  
2. This measurement represents the die capacitance at the pad, not including the package.  
3. Maximum value specified for worst case process at 25°C.  
4. Termination resistance to a V  
/2 level.  
CCO  
(1)(2)  
Table 4: V Maximum Allowed AC Voltage Overshoot and Undershoot for 3.3V HR I/O Banks  
IN  
AC Voltage Overshoot  
% of UI at –55°C to 125°C  
AC Voltage Undershoot  
% of UI at –55°C to 125°C  
–0.40  
–0.45  
–0.50  
–0.55  
–0.60  
–0.65  
–0.70  
–0.75  
–0.80  
–0.85  
–0.90  
–0.95  
100  
61.7  
25.8  
11.0  
4.77  
2.10  
0.94  
0.43  
0.20  
0.09  
0.04  
0.02  
VCCO + 0.55  
100  
VCCO + 0.60  
VCCO + 0.65  
VCCO + 0.70  
46.6  
21.2  
9.75  
4.55  
2.15  
1.02  
0.49  
0.24  
VCCO + 0.75  
V
CCO + 0.80  
CCO + 0.85  
V
VCCO + 0.90  
CCO + 0.95  
V
Notes:  
1. A total of 200 mA per bank should not be exceeded.  
2. The peak voltage of the overshoot or undershoot, and the duration above V  
in this table.  
+ 0.20V or below GND – 0.30V, must not exceed the values  
CCO  
(1)(2)  
Table 5: V Maximum Allowed AC Voltage Overshoot and Undershoot for 1.8V HP I/O Banks  
IN  
AC Voltage Overshoot  
VCCO + 0.55  
% of UI at –55°C to 125°C  
AC Voltage Undershoot  
% of UI at –55°C to 125°C  
100  
50.0(3)  
50.0(3)  
47.0  
–0.55  
–0.60  
–0.65  
–0.70  
–0.75  
100  
VCCO + 0.60  
50.0(3)  
50.0(3)  
50.0(3)  
50.0(3)  
VCCO + 0.65  
VCCO + 0.70  
VCCO + 0.75  
21.2  
DS182 (v2.8) March 4, 2014  
Product Specification  
www.xilinx.com  
Send Feedback  
4
 
 
 
 
 
 
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