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XC7A15T-1CSG325C PDF预览

XC7A15T-1CSG325C

更新时间： 2024-11-01 19:08:59
品牌 Logo 应用领域
赛灵思 - XILINX 栅可编程逻辑
页数 文件大小 规格书
18页 463K
描述
Field Programmable Gate Array, 1300 CLBs, PBGA325, BGA-325

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XC7A15T-1CSG325C 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：LFBGA,Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：12 weeks风险等级：2.31
CLB-Max的组合延迟：1.27 nsJESD-30 代码：S-PBGA-B325
JESD-609代码：e1长度：15 mm
可配置逻辑块数量：1300端子数量：325
最高工作温度：85 °C最低工作温度：
组织：1300 CLBS封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY座面最大高度：1.5 mm
最大供电电压：1.05 V最小供电电压：0.95 V
标称供电电压：1 V表面贴装：YES
温度等级：OTHER端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：15 mmBase Number Matches：1

XC7A15T-1CSG325C 数据手册

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18  
7 Series FPGAs Data Sheet: Overview  
DS180 (v2.6) February 27, 2018  
Product Specification  
General Description  
Xilinx® 7 series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor,  
cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding  
high-performance applications. The 7 series FPGAs include:  
•
•
Spartan®-7 Family: Optimized for low cost, lowest power, and high  
I/O performance. Available in low-cost, very small form-factor  
packaging for smallest PCB footprint.  
•
Kintex®-7 Family: Optimized for best price-performance with a 2X  
improvement compared to previous generation, enabling a new class  
of FPGAs.  
Artix®-7 Family: Optimized for low power applications requiring serial  
transceivers and high DSP and logic throughput. Provides the lowest  
total bill of materials cost for high-throughput, cost-sensitive  
applications.  
•
Virtex®-7 Family: Optimized for highest system performance and  
capacity with a 2X improvement in system performance. Highest  
capability devices enabled by stacked silicon interconnect (SSI)  
technology.  
Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an  
unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less  
power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.  
Summary of 7 Series FPGA Features  
•
•
•
•
Advanced high-performance FPGA logic based on real 6-input look-  
up table (LUT) technology configurable as distributed memory.  
•
Powerful clock management tiles (CMT), combining phase-locked  
loop (PLL) and mixed-mode clock manager (MMCM) blocks for high  
precision and low jitter.  
Quickly deploy embedded processing with MicroBlaze™ processor.  
Integrated block for PCI Express® (PCIe), for up to x8 Gen3  
Endpoint and Root Port designs.  
Wide variety of configuration options, including support for  
commodity memories, 256-bit AES encryption with HMAC/SHA-256  
authentication, and built-in SEU detection and correction.  
Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-  
chip packaging offering easy migration between family members in  
the same package. All packages available in Pb-free and selected  
packages in Pb option.  
Designed for high performance and lowest power with 28 nm,  
HKMG, HPL process, 1.0V core voltage process technology and  
0.9V core voltage option for even lower power.  
36 Kb dual-port block RAM with built-in FIFO logic for on-chip data  
buffering.  
High-performance SelectIO™ technology with support for DDR3  
interfaces up to 1,866 Mb/s.  
High-speed serial connectivity with built-in multi-gigabit transceivers  
from 600 Mb/s to max. rates of 6.6 Gb/s up to 28.05 Gb/s, offering a  
special low-power mode, optimized for chip-to-chip interfaces.  
•
•
•
•
•
•
A user configurable analog interface (XADC), incorporating dual  
12-bit 1MSPS analog-to-digital converters with on-chip thermal and  
supply sensors.  
DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder  
for high-performance filtering, including optimized symmetric  
coefficient filtering.  
•
Table 1: 7 Series Families Comparison  
Max. Capability  
Logic Cells  
Spartan-7  
Artix-7  
215K  
Kintex-7  
478K  
Virtex-7  
1,955K  
102K  
Block RAM(1)  
4.2 Mb  
13 Mb  
34 Mb  
68 Mb  
DSP Slices  
160  
740  
1,920  
3,600  
DSP Performance(2)  
MicroBlaze CPU(3)  
Transceivers  
176 GMAC/s  
929 GMAC/s  
303 DMIPs  
16  
2,845 GMAC/s  
438 DMIPs  
32  
5,335 GMAC/s  
441 DMIPs  
96  
260 DMIPs  
–
Transceiver Speed  
Serial Bandwidth  
PCIe Interface  
Memory Interface  
I/O Pins  
–
6.6 Gb/s  
211 Gb/s  
x4 Gen2  
1,066 Mb/s  
500  
12.5 Gb/s  
800 Gb/s  
x8 Gen2  
1,866 Mb/s  
500  
28.05 Gb/s  
2,784 Gb/s  
x8 Gen3  
1,866 Mb/s  
1,200  
–
–
800 Mb/s  
400  
I/O Voltage  
1.2V–3.3V  
1.2V–3.3V  
1.2V–3.3V  
1.2V–3.3V  
Low-Cost, Wire-Bond,  
Bare-Die Flip-Chip  
Bare-Die Flip-Chip and High-  
Performance Flip-Chip  
Highest Performance  
Flip-Chip  
Package Options  
Low-Cost, Wire-Bond  
Notes:  
1.  
2.  
3.  
Additional memory available in the form of distributed RAM.  
Peak DSP performance numbers are based on symmetrical filter implementation.  
Peak MicroBlaze CPU performance numbers based on microcontroller preset.  
© Copyright 2010–2018 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx  
in the United States and other countries. PCI Express is a trademark of PCI-SIG and used under license. All other trademarks are the property of their respective owners.  
DS180 (v2.6) February 27, 2018  
www.xilinx.com  
Product Specification  
1
 
 
 
 
 
 
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