11
Spartan-6 Family Overview
DS160 (v2.0) October 25, 2011
Product Specification
General Description
The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The
thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous
Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that
delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input look-
up table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation
DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, power-
optimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management
modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a low-
cost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for
high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the
programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable
designers to focus on innovation as soon as their development cycle begins.
Summary of Spartan-6 FPGA Features
•
Spartan-6 Family:
•
Integrated Memory Controller blocks
•
•
Spartan-6 LX FPGA: Logic optimized
Spartan-6 LXT FPGA: High-speed serial connectivity
•
•
•
DDR, DDR2, DDR3, and LPDDR support
Data rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)
Multi-port bus structure with independent FIFO to reduce
design timing issues
•
Designed for low cost
•
•
•
•
Multiple efficient integrated blocks
Optimized selection of I/O standards
Staggered pads
•
Abundant logic resources with increased logic capacity
•
•
Optional shift register or distributed RAM support
Efficient 6-input LUTs improve performance and
minimize power
High-volume plastic wire-bonded packages
•
Low static and dynamic power
•
LUT with dual flip-flops for pipeline centric applications
•
•
•
45 nm process optimized for cost and low power
Hibernate power-down mode for zero power
Suspend mode maintains state and configuration with
multi-pin wake-up, control enhancement
Lower-power 1.0V core voltage (LX FPGAs, -1L only)
High performance 1.2V core voltage (LX and LXT
FPGAs, -2, -3, and -3N speed grades)
•
•
Block RAM with a wide range of granularity
•
•
Fast block RAM with byte write enable
18 Kb blocks that can be optionally programmed as two
independent 9 Kb block RAMs
•
•
Clock Management Tile (CMT) for enhanced performance
•
•
Low noise, flexible clocking
Digital Clock Managers (DCMs) eliminate clock skew
and duty cycle distortion
Phase-Locked Loops (PLLs) for low-jitter clocking
Frequency synthesis with simultaneous multiplication,
division, and phase shifting
•
•
Multi-voltage, multi-standard SelectIO™ interface banks
•
•
•
•
•
•
Up to 1,080 Mb/s data transfer rate per differential I/O
Selectable output drive, up to 24 mA per pin
3.3V to 1.2V I/O standards and protocols
Low-cost HSTL and SSTL memory interfaces
Hot swap compliance
•
•
•
Sixteen low-skew global clock networks
Adjustable I/O slew rates to improve signal integrity
•
•
Simplified configuration, supports low-cost standards
High-speed GTP serial transceivers in the LXT FPGAs
•
•
•
•
2-pin auto-detect configuration
•
•
Up to 3.2 Gb/s
Broad third-party SPI (up to x4) and NOR flash support
Feature rich Xilinx Platform Flash with JTAG
MultiBoot support for remote upgrade with multiple
bitstreams, using watchdog protection
High-speed interfaces including: Serial ATA, Aurora,
1G Ethernet, PCI Express, OBSAI, CPRI, EPON,
GPON, DisplayPort, and XAUI
•
•
Integrated Endpoint block for PCI Express designs (LXT)
Enhanced security for design protection
Low-cost PCI® technology support compatible with the
33 MHz, 32- and 64-bit specification.
•
•
Unique Device DNA identifier for design authentication
AES bitstream encryption in the larger devices
•
•
Faster embedded processing with enhanced, low cost,
MicroBlaze™ soft processor
Industry-leading IP and reference designs
•
Efficient DSP48A1 slices
•
•
•
•
High-performance arithmetic and signal processing
Fast 18 x 18 multiplier and 48-bit accumulator
Pipelining and cascading capability
Pre-adder to assist filter applications
© 2009–2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States
and other countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS160 (v2.0) October 25, 2011
www.xilinx.com
Product Specification
1
5秒后页面跳转
英伟达新AI芯片Rubin或提前半年亮相
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
三星深化印度制造布局，供应链本地化进程加速
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
替代型号
如果您发现信息不准确，
