XC6101~XC6107, XC6111~XC6117 Series
ETR0207_010
Voltage Detector (VDF=1.6V~5.0V)
■GENERAL DESCRIPTION
The XC6101~XC6107, XC6111~XC6117 series are groups of high-precision, low current consumption voltage detectors with
manual reset input and watchdog functions incorporating CMOS process technology. The series consist of a reference
voltage source, delay circuit, comparator, and output driver. With the built-in delay circuit, the XC6101 ~ XC6107, XC6111 ~
XC6117 series do not require any external components to output signals with release delay time. Moreover, with the manual
reset function, reset can be asserted at any time. The ICs produce two types of output; VDFL (low when detected) and VDFH
(high when detected). With the XC6101 ~ XC6105, XC6111 ~ XC6115 series, the WD pin can be left open if the watchdog
function is not used. Whenever the watchdog pin is opened, the internal counter clears before the watchdog timeout occurs.
Since the manual reset pin is internally pulled up to the VIN pin voltage level, the ICs can be used by leaving the manual reset
pin unconnected if the pin is unused. The detect voltages are internally fixed 1.6V ~ 5.0V in increments of 100mV, using laser
trimming technology. Six watchdog timeout periods are available in a range from 6.25ms to 1.6s. Seven release delay times
are available in a range from 3.13ms to 1.6s.
■APPLICATIONS
■FEATURES
Detect Voltage Range
: 1.6V ~ 5.0V, +2%
(100mV increments)
: VDF x 5%, TYP.
●Microprocessor reset circuits
●Memory battery backup circuits
●System power-on reset circuits
●Power failure detection
Hysteresis Width
(XC6101~XC6107)
VDF x 0.1%, TYP.
(XC6111~XC6117)
Operating Voltage Range : 1.0V ~ 6.0V
Detect Voltage Temperature: +100ppm/OC (TYP.)
Coefficient
Output Configuration
: N-channel open drain,
CMOS
Reset Output Options
: VDFL (Low when detected)
VDFH (High when detected)
Watchdog Function
: Watchdog input WD;
If it remains ether high or low for
the duration of the watchdog
timeout period,
a
reset is
asserted.
Manual Reset Function
Release Delay Time
: Manual Reset Input MRB;
When it changes from high to
low, a reset is asserted.
: 1.6s, 400ms, 200ms, 100ms,
50ms, 25ms, 3.13ms (TYP.)
Watchdog Timeout Period : 1.6s, 400ms, 200ms, 100ms,
50ms, 6.25ms (TYP.)
Packages
: SOT-25, USP-6C
■TYPICAL APPLICATION CIRCUIT
■TYPICAL PERFORMANCE
CHARACTERISTICS
●Supply Current vs. Input Voltage
μP
VIN
XC61X1~XC61X5 (2.7V)
30
VIN
XC6101/XC6102
Rpull*
25
RESETB
INPUT
VIN
RESETB
20
Ta=25
MRB
WD
I/O
℃
Ta=85
℃
15
10
5
VSS
VSS
Ta=-40
5
℃
0
0
1
2
3
4
6
* Not necessary with CMOS output products.
Input Voltage: VIN (V)
ꢀ
* ‘x’ represents both ‘0’ and ‘1’. (ex. XC61x1⇒XC6101 and XC6111)
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