0
XC5200 Series
R
Field Programmable Gate Arrays
0
7*
November 5, 1998 (Version 5.2)
Product Specification
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Footprint compatibility in common packages within
the XC5200 Series and with the XC4000 Series
Over 150 device/package combinations, including
advanced BGA, TQ, and VQ packaging available
Features
• Low-cost, register/latch rich, SRAM based
reprogrammable architecture
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0.5µm three-layer metal CMOS process technology
256 to 1936 logic cells (3,000 to 23,000 “gates”)
Price competitive with Gate Arrays
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Fully Supported by Xilinx Development System
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Automatic place and route software
Wide selection of PC and Workstation platforms
Over 100 3rd-party Alliance interfaces
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System Level Features
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System performance beyond 50 MHz
6 levels of interconnect hierarchy
VersaRing™ I/O Interface for pin-locking
Dedicated carry logic for high-speed arithmetic
functions
Supported by shrink-wrap Foundation software
Description
The XC5200 Field-Programmable Gate Array Family is
engineered to deliver low cost. Building on experiences
gained with three previous successful SRAM FPGA fami-
lies, the XC5200 family brings a robust feature set to pro-
grammable logic design. The VersaBlock™ logic module,
the VersaRing I/O interface, and a rich hierarchy of inter-
connect resources combine to enhance design flexibility
and reduce time-to-market. Complete support for the
XC5200 family is delivered through the familiar Xilinx soft-
ware environment. The XC5200 family is fully supported on
popular workstation and PC platforms. Popular design
entry methods are fully supported, including ABEL, sche-
matic capture, VHDL, and Verilog HDL synthesis. Design-
ers utilizing logic synthesis can use their existing tools to
design with the XC5200 devices.
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Cascade chain for wide input functions
Built-in IEEE 1149.1 JTAG boundary scan test
circuitry on all I/O pins
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Internal 3-state bussing capability
Four dedicated low-skew clock or signal distribution
nets
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Versatile I/O and Packaging
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Innovative VersaRing™ I/O interface provides a high
logic cell to I/O ratio, with up to 244 I/O signals
Programmable output slew-rate control maximizes
performance and reduces noise
Zero Flip-Flop hold time for input registers simplifies
system timing
Independent Output Enables for external bussing
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Table 1: XC5200 Field-Programmable Gate Array Family Members
Device
XC5202
XC5204
480
XC5206
784
XC5210
1,296
XC5215
1,936
Logic Cells
256
3,000
2,000 - 3,000
8 x 8
Max Logic Gates
Typical Gate Range
VersaBlock Array
CLBs
6,000
4,000 - 6,000
10 x 12
120
10,000
16,000
23,000
6,000 - 10,000 10,000 - 16,000 15,000 - 23,000
14 x 14
196
18 x 18
324
22 x 22
484
64
Flip-Flops
256
480
784
1,296
196
1,936
244
I/Os
84
124
148
TBUFs per Longline
10
14
16
20
24
November 5, 1998 (Version 5.2)
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