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XC4005XL-2TQG144C PDF预览

XC4005XL-2TQG144C

更新时间： 2024-11-10 19:37:15
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
68页 982K
描述
Field Programmable Gate Array, 196 CLBs, 3000 Gates, 179MHz, CMOS, PQFP144, PLASTIC, TQFP-144

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XC4005XL-2TQG144C 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：QFP包装说明：LFQFP,
针数：144Reach Compliance Code：compliant
风险等级：5.79Is Samacsys：N
其他特性：MAX USABLE 5000 LOGIC GATES最大时钟频率：179 MHz
CLB-Max的组合延迟：1.5 nsJESD-30 代码：S-PQFP-G144
JESD-609代码：e3长度：20 mm
湿度敏感等级：3可配置逻辑块数量：196
等效关口数量：3000端子数量：144
最高工作温度：85 °C最低工作温度：
组织：196 CLBS, 3000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：20 mmBase Number Matches：1

XC4005XL-2TQG144C 数据手册

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Product Obsolete or Under Obsolescence  
0
R
XC4000E and XC4000X Series Field  
Programmable Gate Arrays  
0
0*  
May 14, 1999 (Version 1.6)  
Product Specification  
XC4000E and XC4000X Series  
Features  
Low-Voltage Versions Available  
•
•
Low-Voltage Devices Function at 3.0 - 3.6 Volts  
XC4000XL: High Performance Low-Voltage Versions of  
XC4000EX devices  
Note: Information in this data sheet covers the XC4000E,  
XC4000EX, and XC4000XL families. A separate data sheet  
covers the XC4000XLA and XC4000XV families. Electrical  
Specifications and package/pin information are covered in  
separate sections for each family to make the information  
easier to access, review, and print. For access to these sec-  
tions, see the Xilinx web site at  
Additional XC4000X Series Features  
•
•
•
•
•
High Performance — 3.3 V XC4000XL  
High Capacity — Over 180,000 Usable Gates  
5 V tolerant I/Os on XC4000XL  
0.35 µm SRAM process for XC4000XL  
Additional Routing Over XC4000E  
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp  
•
System featured Field-Programmable Gate Arrays  
-
-
almost twice the routing capacity for high-density  
designs  
SelectRAMTM memory: on-chip ultra-fast RAM with  
-
-
synchronous write option  
dual-port RAM option  
•
•
Buffered Interconnect for Maximum Speed Blocks  
Improved VersaRingTM I/O Interconnect for Better Fixed  
Pinout Flexibility  
-
-
-
-
-
-
-
-
Fully PCI compliant (speed grades -2 and faster)  
Abundant flip-flops  
Flexible function generators  
Dedicated high-speed carry logic  
Wide edge decoders on each edge  
Hierarchy of interconnect lines  
Internal 3-state bus capability  
Eight global low-skew clock or signal distribution  
networks  
6
•
•
12 mA Sink Current Per XC4000X Output  
Flexible New High-Speed Clock Network  
-
-
Eight additional Early Buffers for shorter clock delays  
Virtually unlimited number of clock signals  
•
•
Optional Multiplexer or 2-input Function Generator on  
Device Outputs  
Four Additional Address Bits in Master Parallel  
Configuration Mode  
•
•
•
•
System Performance beyond 80 MHz  
Flexible Array Architecture  
Low Power Segmented Routing Architecture  
Systems-Oriented Features  
Introduction  
-
IEEE 1149.1-compatible boundary scan logic  
support  
XC4000 Series high-performance, high-capacity Field Pro-  
grammable Gate Arrays (FPGAs) provide the benefits of  
custom CMOS VLSI, while avoiding the initial cost, long  
development cycle, and inherent risk of a conventional  
masked gate array.  
-
-
-
Individually programmable output slew rate  
Programmable input pull-up or pull-down resistors  
12 mA sink current per XC4000E output  
•
•
Configured by Loading Binary File  
Unlimited re-programmability  
Read Back Capability  
-
The result of thirteen years of FPGA design experience and  
feedback from thousands of customers, these FPGAs com-  
bine architectural versatility, on-chip Select-RAM memory  
with edge-triggered and dual-port modes, increased  
speed, abundant routing resources, and new, sophisticated  
software to achieve fully automated implementation of  
complex, high-density, high-performance designs.  
-
-
Program verification  
Internal node observability  
•
•
Backward Compatible with XC4000 Devices  
Development System runs on most common computer  
platforms  
-
-
-
Interfaces to popular design environments  
Fully automatic mapping, placement and routing  
Interactive design editor for design optimization  
The XC4000E and XC4000X Series currently have 20  
members, as shown in Table 1.  
May 14, 1999 (Version 1.6)  
6-5  
1234567...68

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