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XC4002XL-2PQ100I

更新时间： 2024-11-09 22:12:27
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赛灵思 - XILINX 现场可编程门阵列栅
页数 文件大小 规格书
4页 25K
描述
XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4002XL-2PQ100I 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：PLASTIC, QFP-100
针数：100Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.85
其他特性：MAX USABLE 1600 LOGIC GATES最大时钟频率：179 MHz
CLB-Max的组合延迟：1.5 nsJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
湿度敏感等级：3可配置逻辑块数量：64
等效关口数量：1000输入次数：64
逻辑单元数量：64输出次数：64
端子数量：100组织：64 CLBS, 1000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP100,.7X.9封装形状：RECTANGULAR
封装形式：FLATPACK电源：3.3 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：3.4 mm子类别：Field Programmable Gate Arrays
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

XC4002XL-2PQ100I 数据手册

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XC4000E  
Logic Cell Array Family  
Product Preview  
Features  
Description  
The XC4000E family of Field-Programmable Gate Arrays  
(FPGAs) provides the benefits of custom CMOS VLSI,  
while avoiding the initial cost, time delay, and inherent risk  
of a conventional masked gate array.  
• Third Generation Field-Programmable Gate Arrays  
– On-chip ultra-fast RAM with synchronous write option  
– Dual-port RAM option  
– Fully PCI compliant  
– Abundant flip-flops  
The XC4000E family provides a regular, flexible, pro-  
grammable architecture of Configurable Logic Blocks  
(CLBs), interconnected by a powerful hierarchy of versa-  
tile routing resources, and surrounded by a perimeter of  
programmable Input/Output Blocks (IOBs).  
– Flexible function generators  
– Dedicated high-speed carry-propagation circuit  
– Wide edge decoders (four per edge)  
– Hierarchy of interconnect lines  
– Internal 3-state bus capability  
XC4000E devices have generous routing resources to  
accommodate the most complex interconnect patterns.  
They are customized by loading configuration data into  
the internal memory cells. The FPGA can either actively  
read its configuration data out of external serial or byte-  
parallel PROM (master modes), or the configuration data  
can be written into the FPGA (slave and peripheral  
modes).  
– 8 global low-skew clock or signal distribution network  
• Flexible Array Architecture  
– Programmable logic blocks and I/O blocks  
– Programmable interconnects and wide decoders  
• Sub-micron CMOS Process  
– High-speed logic and Interconnect  
– Low power consumption  
• Systems-Oriented Features  
The XC4000E family is supported by powerful and sophis-  
ticated software, covering every aspect of design: from  
schematic entry, to simulation, to automatic block place-  
ment and routing of interconnects, and finally the creation  
of the configuration bit stream.  
– IEEE 1149.1-compatible boundary-scan logic support  
– Programmable output slew rate (2 modes)  
– Programmable input pull-up or pull-down resistors  
– 12-mA sink current per output  
– 24-mA sink current per output pair  
FPGAs are ideal for shortening the design and develop-  
ment cycle, but they also offer a cost-effective solution for  
production rates well beyond 1,000 systems per month.  
• Configured by Loading Binary File  
– Unlimited reprogrammability  
– Six programming modes  
The XC4000E family is a superset of the popular XC4000  
family. For a detailed description of the device architec-  
ture, configuration methods, pin functionality, package  
pin-outs and dimensions, see the Xilinx Programmable  
Logic Data Book.  
• XACT Development System runs on ’386/’486/  
Pentium-type PC, Apollo, Sun-4, and Hewlett-Packard  
700 series  
– Interfaces to popular design environments like  
Viewlogic, Mentor Graphics and OrCAD  
– Fully automatic partitioning, placement and routing  
– Interactive design editor for design optimization  
– 288 macros, 34 hard macros, RAM/ROM compiler  
The following pages describes the new features of the  
XC4000E family and list electrical and timing parameters.  
Table 1. The XC4000E Family of Field-Programmable Gate Arrays  
Device  
XC4003E XC4005E  
XC4006E  
XC4008E XC4010E  
XC4013E  
XC4020E XC4025E  
Appr. Gate Count  
CLB Matrix  
Number of CLBs  
Number of Flip-Flops  
Max Decode Inputs (per side)  
Max RAM Bits  
3,000  
10 x 10  
100  
360  
30  
5,000  
14 x 14  
196  
616  
42  
6,000  
16 x 16  
256  
768  
48  
8,000  
18 x 18  
324  
936  
54  
10,000  
20 x 20  
400  
1,120  
60  
13,000  
24 x 24  
576  
1,536  
72  
20,000  
28 x 28  
784  
2,016  
84  
25,000  
32 x 32  
1,024  
2,560  
96  
3,200  
80  
6,272  
112  
8,192  
128  
10,368  
144  
12,800  
160  
18,432  
192  
25,088  
224  
32,768  
256  
Number of IOBs  
1
1234

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