5秒后页面跳转
XC3S500E-4FGG320CS1 PDF预览

XC3S500E-4FGG320CS1

更新时间: 2024-11-19 15:23:47
品牌 Logo 应用领域
赛灵思 - XILINX 时钟可编程逻辑
页数 文件大小 规格书
227页 6528K
描述
Field Programmable Gate Array, 572MHz, 10476-Cell, CMOS, PBGA320,

XC3S500E-4FGG320CS1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:BGA, BGA320,18X18,40
Reach Compliance Code:unknownECCN代码:3A991.D
HTS代码:8542.39.00.01风险等级:5.26
最大时钟频率:572 MHzCLB-Max的组合延迟:0.76 ns
JESD-30 代码:S-PBGA-B320JESD-609代码:e1
长度:19 mm湿度敏感等级:3
可配置逻辑块数量:1164等效关口数量:500000
输入次数:232逻辑单元数量:10476
输出次数:176端子数量:320
最高工作温度:85 °C最低工作温度:
组织:1164 CLBS, 500000 GATES封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA320,18X18,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):260电源:1.2,1.2/3.3,2.5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:2 mm子类别:Field Programmable Gate Arrays
最大供电电压:1.26 V最小供电电压:1.14 V
标称供电电压:1.2 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:19 mm
Base Number Matches:1

XC3S500E-4FGG320CS1 数据手册

 浏览型号XC3S500E-4FGG320CS1的Datasheet PDF文件第2页浏览型号XC3S500E-4FGG320CS1的Datasheet PDF文件第3页浏览型号XC3S500E-4FGG320CS1的Datasheet PDF文件第4页浏览型号XC3S500E-4FGG320CS1的Datasheet PDF文件第5页浏览型号XC3S500E-4FGG320CS1的Datasheet PDF文件第6页浏览型号XC3S500E-4FGG320CS1的Datasheet PDF文件第7页 
1
Spartan-3E FPGA Family  
Data Sheet  
DS312 December 14, 2018  
Product Specification  
Module 1:  
Introduction and Ordering Information  
Module 3:  
DC and Switching Characteristics  
DS312 (v4.2) December 14, 2018  
DS312 (v4.2) December 14, 2018  
Introduction  
DC Electrical Characteristics  
Features  
Absolute Maximum Ratings  
Supply Voltage Specifications  
Recommended Operating Conditions  
DC Characteristics  
Architectural Overview  
Package Marking  
Ordering Information  
Switching Characteristics  
Module 2:  
I/O Timing  
Functional Description  
SLICE Timing  
DS312 (v4.2) December 14, 2018  
DCM Timing  
Input/Output Blocks (IOBs)  
Block RAM Timing  
Multiplier Timing  
Configuration and JTAG Timing  
Overview  
SelectIO™ Signal Standards  
Configurable Logic Block (CLB)  
Block RAM  
Module 4:  
Pinout Descriptions  
DS312 (v4.2) December 14, 2018  
Dedicated Multipliers  
Digital Clock Manager (DCM)  
Clock Network  
Pin Descriptions  
Package Overview  
Pinout Tables  
Configuration  
Powering Spartan®-3E FPGAs  
Production Stepping  
Footprint Diagrams  
© Copyright 2005–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx  
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.  
DS312 December 14, 2018  
www.xilinx.com  
Product Specification  
1

与XC3S500E-4FGG320CS1相关器件

型号 品牌 获取价格 描述 数据表
XC3S500E-4FGG320I XILINX

获取价格

Spartan-3E FPGA Family
XC3S500E-4FGG400C XILINX

获取价格

Spartan-3E FPGA Family
XC3S500E-4FGG400I XILINX

获取价格

Spartan-3E FPGA Family
XC3S500E-4FGG484C XILINX

获取价格

Spartan-3E FPGA Family
XC3S500E-4FGG484I XILINX

获取价格

Spartan-3E FPGA Family
XC3S500E-4FT256C XILINX

获取价格

Spartan-3E FPGA Family
XC3S500E-4FT256CS1 XILINX

获取价格

Field Programmable Gate Array, 572MHz, 10476-Cell, CMOS, PBGA256,
XC3S500E-4FT256I XILINX

获取价格

Spartan-3E FPGA Family
XC3S500E-4FT256IS1 XILINX

获取价格

Field Programmable Gate Array, 572MHz, 10476-Cell, CMOS, PBGA256,
XC3S500E-4FTG256C XILINX

获取价格

Spartan-3E FPGA Family