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XC3S500E-4PQ208C PDF预览

XC3S500E-4PQ208C

更新时间: 2024-11-19 04:24:15
品牌 Logo 应用领域
赛灵思 - XILINX /
页数 文件大小 规格书
193页 1733K
描述
Spartan-3E FPGA Family

XC3S500E-4PQ208C 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:FQFP, QFP208,1.2SQ,20针数:208
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:12 weeks
风险等级:1.51最大时钟频率:572 MHz
CLB-Max的组合延迟:0.76 nsJESD-30 代码:S-PQFP-G208
JESD-609代码:e0长度:28 mm
湿度敏感等级:3可配置逻辑块数量:1164
等效关口数量:500000输入次数:158
逻辑单元数量:10476输出次数:126
端子数量:208最高工作温度:85 °C
最低工作温度:组织:1164 CLBS, 500000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装等效代码:QFP208,1.2SQ,20封装形状:SQUARE
封装形式:FLATPACK, FINE PITCH峰值回流温度(摄氏度):225
电源:1.2,1.2/3.3,2.5 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:4.1 mm
子类别:Field Programmable Gate Arrays最大供电电压:1.26 V
最小供电电压:1.14 V标称供电电压:1.2 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:28 mmBase Number Matches:1

XC3S500E-4PQ208C 数据手册

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Spartan-3E FPGA Family:  
Complete Data Sheet  
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DS312 March 21, 2005  
Module 1:  
Introduction and Ordering Information  
Module 3:  
DC and Switching Characteristics  
DS312-1 (v1.1) March 21, 2005  
6 pages  
DS312-3 (v1.0) March 1, 2005  
18 pages  
Introduction  
DC Electrical Characteristics  
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-
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Absolute Maximum Ratings  
Supply Voltage Specifications  
Recommended Operating Conditions  
DC Characteristics  
Features  
Architectural Overview  
Package Marking  
Ordering Information  
Switching Characteristics  
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DCM Timing  
Configuration and JTAG Timing  
Module 2:  
Functional Description  
DS312-2 (v1.1) March 21, 2005  
96 pages  
Module 4:  
Pinout Descriptions  
Input/Output Blocks (IOBs)  
DS312-4 (v1.1) March 21, 2005  
72 pages  
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Overview  
SelectIO™ Signal Standards  
Pin Descriptions  
Package Overview  
Pinout Tables  
Configurable Logic Block (CLB)  
Block RAM  
Dedicated Multipliers  
Digital Clock Manager (DCM)  
Clock Network  
Footprint Diagrams  
Configuration  
Powering Spartan-3E FPGAs  
IMPORTANT NOTE: The Spartan-3E FPGA data sheet is created and published in separate modules. This complete  
version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin  
at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy  
navigation in this volume.  
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.  
All other trademarks are the property of their respective owners.  
DS312 March 21, 2005  
www.xilinx.com  
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