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XC3S4000-4CPG132I PDF预览

XC3S4000-4CPG132I

更新时间： 2024-11-08 04:24:15
品牌 Logo 应用领域
赛灵思 - XILINX 现场可编程门阵列可编程逻辑
页数 文件大小 规格书
198页 1762K
描述
Spartan-3 FPGA Family: Complete Data Sheet

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XC3S4000-4CPG132I 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：TFBGA,针数：132
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.77Is Samacsys：N
JESD-30 代码：S-PBGA-B132长度：8 mm
可配置逻辑块数量：192等效关口数量：50000
端子数量：132组织：192 CLBS, 50000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装形状：SQUARE封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：1.1 mm最大供电电压：1.26 V
最小供电电压：1.14 V标称供电电压：1.2 V
表面贴装：YES端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
宽度：8 mmBase Number Matches：1

XC3S4000-4CPG132I 数据手册

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Spartan-3 FPGA Family:  
Complete Data Sheet  
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DS099 January 17, 2005  
This document includes all four modules of the Spartan™-3 FPGA data sheet.  
Module 1:  
Introduction and Ordering Information  
Module 3:  
DC and Switching Characteristics  
DS099-1 (v1.4) January 17, 2005  
6 pages  
DS099-3 (v1.5) December 17, 2004  
39 pages  
•
•
•
•
•
•
Introduction  
•
DC Electrical Characteristics  
-
-
-
-
Absolute Maximum Ratings  
Supply Voltage Specifications  
Recommended Operating Conditions  
DC Characteristics  
Features  
Architectural Overview  
Product Availability  
User I/O Chart  
•
Switching Characteristics  
Ordering Information  
-
-
-
-
I/O Timing  
Internal Logic Timing  
DCM Timing  
Module 2:  
Functional Description  
DS099-2 (v1.3) August 24, 2004  
40 pages  
Configuration and JTAG Timing  
Module 4:  
Pinout Descriptions  
DS099-4 (v1.6) January 17, 2005  
112 pages  
•
IOBs  
-
-
IOB Overview  
SelectIO™ Signal Standards  
•
•
•
•
CLB Overview  
•
Pin Descriptions  
Pin Behavior During Configuration  
Block RAM  
Dedicated Multipliers  
Digital Clock Manager (DCM)  
-
•
•
Package Overview  
Pinout Tables  
-
Clock Network  
-
Footprints  
•
Configuration  
IMPORTANT NOTE: The Spartan-3 FPGA data sheet is created and published in separate modules. This complete version  
is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin at 1 for  
each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy navigation in  
this volume.  
© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS099 January 17, 2005  
www.xilinx.com  
1234567...198

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