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XC2V3000-6FF1152I PDF预览

XC2V3000-6FF1152I

更新时间： 2024-11-07 22:31:51
品牌 Logo 应用领域
赛灵思 - XILINX 现场可编程门阵列可编程逻辑栅时钟
页数 文件大小 规格书
7页 128K
描述
Virtex-II 1.5V Field-Programmable Gate Arrays

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中文翻译

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XC2V3000-6FF1152I 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：35 X 35 MM, 1 MM PITCH, MS-034AAR-1, FLIP CHIP, FBGA-1152针数：1152
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.82Is Samacsys：N
最大时钟频率：820 MHzCLB-Max的组合延迟：0.35 ns
JESD-30 代码：S-PBGA-B1152JESD-609代码：e0
长度：35 mm湿度敏感等级：4
可配置逻辑块数量：3584等效关口数量：3000000
输入次数：720逻辑单元数量：32256
输出次数：720端子数量：1152
组织：3584 CLBS, 3000000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA1152,34X34,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：225电源：1.5,1.5/3.3,3.3 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：3.4 mm子类别：Field Programmable Gate Arrays
最大供电电压：1.575 V最小供电电压：1.425 V
标称供电电压：1.5 V表面贴装：YES
技术：CMOS端子面层：Tin/Lead (Sn63Pb37)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：35 mmBase Number Matches：1

XC2V3000-6FF1152I 数据手册

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Virtex-II 1.5V  
Field-Programmable Gate Arrays  
0
0
DS031-1 (v1.7) October 2, 2001  
Advance Product Specification  
®
Summary of Virtex -II Features  
•
Industry First Platform FPGA Solution  
-
-
-
Digitally Controlled Impedance (DCI) I/O: on-chip  
termination resistors for single-ended I/O standards  
•
IP-Immersion™ Architecture  
PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz  
compliance, and CardBus compliant  
-
-
-
Densities from 40K to 8M system gates  
420 MHz internal clock speed (Advance Data)  
840+ Mb/s I/O (Advance Data)  
Differential Signaling  
·
840 Mb/s Low-Voltage Differential Signaling I/O  
(LVDS) with current mode drivers  
Bus LVDS I/O  
Lightning Data Transport (LDT) I/O with current  
driver buffers  
•
SelectRAM™ Memory Hierarchy  
-
3 Mb of True Dual-Port™ RAM in 18-Kbit block  
SelectRAM resources  
·
·
-
-
Up to 1.5 Mb of distributed SelectRAM resources  
High-performance interfaces to external memory  
·
Low-Voltage Positive Emitter-Coupled Logic  
(LVPECL) I/O  
·
·
·
·
DDR-SDRAM interface  
FCRAM interface  
QDR™-SRAM interface  
Sigma RAM interface  
·
Built-in DDR Input and Output registers  
-
Proprietary high-performance SelectLink™  
Technology  
·
·
·
High-bandwidth data path  
Double Data Rate (DDR) link  
Web-based HDL generation methodology  
•
•
Arithmetic Functions  
-
-
Dedicated 18-bit x 18-bit multiplier blocks  
Fast look-ahead carry logic chains  
•
•
Supported by Xilinx Foundation™ and Alliance™  
Series Development Systems  
Flexible Logic Resources  
-
Up to 93,184 internal registers / latches with Clock  
-
-
-
Integrated VHDL and Verilog design flows  
Compilation of 10M system gates designs  
Internet Team Design (ITD) tool  
Enable  
-
Up to 93,184 look-up tables (LUTs) or cascadable  
16-bit shift registers  
SRAM-Based In-System Configuration  
-
-
Wide multiplexers and wide-input function support  
-
-
Fast SelectMAP™ configuration  
Horizontal cascade chain and Sum-of-Products  
support  
Triple Data Encryption Standard (DES) security  
option (Bitstream Encryption)  
-
Internal 3-state bussing  
-
-
-
-
IEEE1532 support  
•
High-Performance Clock Management Circuitry  
Partial reconfiguration  
Unlimited re-programmability  
Readback capability  
-
Up to 12 DCM (Digital Clock Manager) modules  
·
·
·
Precise clock de-skew  
Flexible frequency synthesis  
High-resolution phase shifting  
•
•
0.15 µm 8-Layer Metal process with 0.12 µm  
high-speed transistors  
-
16 global clock multiplexer buffers  
1.5 V (VCCINT) core power supply, dedicated 3.3 V  
CCAUX auxiliary and VCCO I/O power supplies  
•
•
Active Interconnect™ Technology  
V
-
-
Fourth generation segmented routing structure  
Predictable, fast routing delay, independent of  
fanout  
•
•
IEEE 1149.1 compatible boundary-scan logic support  
Flip-Chip and Wire-Bond Ball Grid Array (BGA)  
packages in three standard fine pitches (0.80mm,  
1.00mm, and 1.27mm)  
SelectI/O-Ultra™ Technology  
-
-
Up to 1,108 user I/Os  
19 single-ended standards and six differential  
standards  
•
100% factory tested  
-
Programmable sink current (2 mA to 24 mA) per I/O  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS031-1 (v1.7) October 2, 2001  
Advance Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 1 of 4  
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