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XC2V1000-5FGG256I PDF预览

XC2V1000-5FGG256I

更新时间: 2024-11-08 13:20:51
品牌 Logo 应用领域
赛灵思 - XILINX 时钟可编程逻辑
页数 文件大小 规格书
319页 1869K
描述
Field Programmable Gate Array, 1280 CLBs, 1000000 Gates, 750MHz, 11520-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, MO-034AAF-1, FBGA-256

XC2V1000-5FGG256I 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:17 X 17 MM, 1 MM PITCH, LEAD FREE, MO-034AAF-1, FBGA-256针数:256
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.79
最大时钟频率:750 MHzCLB-Max的组合延迟:0.39 ns
JESD-30 代码:S-PBGA-B256JESD-609代码:e1
长度:17 mm湿度敏感等级:3
可配置逻辑块数量:1280等效关口数量:1000000
输入次数:172逻辑单元数量:11520
输出次数:172端子数量:256
组织:1280 CLBS, 1000000 GATES封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA256,16X16,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):260电源:1.5,1.5/3.3,3.3 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:2 mm子类别:Field Programmable Gate Arrays
最大供电电压:1.575 V最小供电电压:1.425 V
标称供电电压:1.5 V表面贴装:YES
技术:CMOS端子面层:Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:17 mmBase Number Matches:1

XC2V1000-5FGG256I 数据手册

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— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —  
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Virtex-II Platform FPGAs:  
Complete Data Sheet  
DS031 (v4.0) April 7, 2014  
Product Specification  
Module 1:  
Introduction and Overview  
Module 3:  
DC and Switching Characteristics  
7 pages  
44 pages  
Summary of Features  
General Description  
Architecture  
Device/Package Combinations and Maximum I/O  
Ordering Examples  
Electrical Characteristics  
Performance Characteristics  
Switching Characteristics  
Pin-to-Pin Output Parameter Guidelines  
Pin-to-Pin Input Parameter Guidelines  
DCM Timing Parameters  
Source-Synchronous Switching Characteristics  
Module 2:  
Functional Description  
Module 4:  
Pinout Information  
40 pages  
Detailed Description  
227 pages  
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Input/Output Blocks (IOBs)  
Digitally Controlled Impedance (DCI)  
Configurable Logic Blocks (CLBs)  
18-Kb Block SelectRAM™ Resources  
18-Bit x 18-Bit Multipliers  
Global Clock Multiplexer Buffers  
Digital Clock Manager (DCM)  
Pin Definitions  
Pinout Tables  
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CS144/CSG144 Chip-Scale BGA Package  
FG256/FGG256 Fine-Pitch BGA Package  
FG456/FGG456 Fine-Pitch BGA Package  
FG676/FGG676 Fine-Pitch BGA Package  
BG575/BGG575 Standard BGA Package  
BG728/BGG728 Standard BGA Package  
FF896 Flip-Chip Fine-Pitch BGA Package  
FF1152 Flip-Chip Fine-Pitch BGA Package  
FF1517 Flip-Chip Fine-Pitch BGA Package  
BF957Flip-Chip BGA Package  
Routing  
Creating a Design  
Configuration  
IMPORTANT NOTE: Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision  
History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.  
© 2000–2014 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other  
trademarks are the property of their respective owners.  
DS031 (v4.0) April 7, 2014  
www.xilinx.com  
Product Specification  
1

XC2V1000-5FGG256I 替代型号

型号 品牌 替代类型 描述 数据表
XC2V1000-5FG256I XILINX

完全替代

Virtex-II 1.5V Field-Programmable Gate Arrays
XC2V1000-4FG256I XILINX

完全替代

Virtex-II 1.5V Field-Programmable Gate Arrays

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