Datasheet > XC2S300E-8

XC2S300E-8

更新时间： 2024-11-07 23:30:31

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中文翻译

获取价格

数据手册

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XC2S300E-8 数据手册

MC-XIL-USB11DEV

USB 1.1 Device Controller

May 20, 2002

Product Specification

AllianceCORE™ Facts

Core Specifics

See Table 1

Provided with Core

Documentation

User manual, Implementation

guide, data sheet

NGO netlist

Simulation model

.ucf

Design File Formats

Verification

Product Line

9980 Huennekens Street

San Diego, CA 92121

Americas:+1 888-360-9044

Europe: +1 41 (0) 32 374 32 00

Constraints File

Instantiation Templates

VHDL, Verilog

None

Reference designs &

application notes

Asia:

E-mail: sales@memecdesign.com

URL: www.memedesign.com

+(852) 2410 2720

Additional Items

Warranty by MemecCore

Design Tool Requirements

Synthesis Tool

Simulation

Synplify Pro 6.0

ModelSim 5.4e

Features

•

Available under terms of the SignOnce IP License

Complies with USB protocol revision 1.1

Supports VCI to the application bus

Supports full-speed (12 Mbps) signaling bit rate

Supports low-speed (1.5 Mbps) signaling bit rate

Handles USB protocol

Handles USB device states

Clock and data recovery from USB

Microprocessor independent

Includes Suspend/Resume logic

Performs cyclic redundancy checks (CRC) with CRC5

checking, and CRC16 generation and checking

Supports up to fifteen configurations, with each

configuration supporting fifteen interfaces and each

interface handling up to fifteen alternate settings

Enables physical endpoint number programming and

supports up to 16 bidirectional logical endpoints

Support

Core support provided by MemecCore

Additional customization provided by Memec Design

Features (contd)

•

Maintains data toggle bits

Enables user-configured endpoint information

Provides understanding and decoding of standard USB

commands to endpoint zero

Provides the option to decode the Get Descriptor

command or to pass the command to the application for

decoding

Supports class/vendor commands by passing the Setup

transactions to the application

Supports up to 15 string descriptors

•

Table 1: Core Implementation Data

Supported

Device Tested

Family

CLB

Slices

Clock

IOBs

Performance

Special

Features

IOBs

Xilinx Tools

(MHz)

Virtex™-II

Spartan™-II

Virtex™-E

Notes:

XC2V1000-5

XC2S200-5

XCV300E-8

1036

1029

117

Alliance 3.3iSP8

None

1. These numbers reached with the following options, with the sample design: hard-coded registers, application and UDC using same

clock, the core does not decode get_descriptor, 1 interface, 1 alternate, 1 additional endpoint (bulk out), endpoint 0 maxpktsize is 8

bytes, endpoint 1 maxpktsize is 8 bytes

2. Assuming all core signals are routed off-chip.

3. Minimum guaranteed speed.

May 20, 2002

12 3 4 5 6

中文翻译

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