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XC2S15-6CSG144C PDF预览

XC2S15-6CSG144C

更新时间: 2024-11-08 07:06:35
品牌 Logo 应用领域
赛灵思 - XILINX 现场可编程门阵列可编程逻辑时钟
页数 文件大小 规格书
99页 1009K
描述
Spartan-II FPGA Family

XC2S15-6CSG144C 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:CHIP SCALE, BGA-144
针数:144Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.79
Is Samacsys:N其他特性:MAXIMUM USABLE GATES 15000
最大时钟频率:263 MHzCLB-Max的组合延迟:0.6 ns
JESD-30 代码:S-PBGA-B144JESD-609代码:e1
长度:12 mm湿度敏感等级:3
可配置逻辑块数量:96等效关口数量:15000
输入次数:90逻辑单元数量:432
输出次数:86端子数量:144
最高工作温度:85 °C最低工作温度:
组织:96 CLBS, 15000 GATES封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA144,13X13,32
封装形状:SQUARE封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.5/3.3,2.5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Field Programmable Gate Arrays
最大供电电压:2.625 V最小供电电压:2.375 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:12 mm
Base Number Matches:1

XC2S15-6CSG144C 数据手册

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Spartan-II FPGA Family  
Data Sheet  
DS001 June 13, 2008  
Product Specification  
This document includes all four modules of the Spartan®-II FPGA data sheet.  
Module 1:  
Introduction and Ordering Information  
Module 3:  
DC and Switching Characteristics  
DS001-1 (v2.8) June 13, 2008  
DS001-3 (v2.8) June 13, 2008  
Introduction  
DC Specifications  
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Absolute Maximum Ratings  
Recommended Operating Conditions  
DC Characteristics  
Power-On Requirements  
DC Input and Output Levels  
Features  
General Overview  
Product Availability  
User I/O Chart  
Ordering Information  
Switching Characteristics  
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Pin-to-Pin Parameters  
Module 2:  
IOB Switching Characteristics  
Clock Distribution Characteristics  
DLL Timing Parameters  
CLB Switching Characteristics  
Block RAM Switching Characteristics  
TBUF Switching Characteristics  
JTAG Switching Characteristics  
Functional Description  
DS001-2 (v2.8) June 13, 2008  
Architectural Description  
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Spartan-II Array  
Input/Output Block  
Configurable Logic Block  
Block RAM  
Clock Distribution: Delay-Locked Loop  
Boundary Scan  
Module 4:  
Pinout Tables  
Development System  
Configuration  
DS001-4 (v2.8) June 13, 2008  
Pin Definitions  
Pinout Tables  
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Configuration Timing  
Design Considerations  
IMPORTANT NOTE: This Spartan-II FPGA data sheet is in four modules. Each module has its own Revision History at the  
end. Use the PDF "Bookmarks" for easy navigation in this volume.  
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other  
trademarks are the property of their respective owners.  
DS001 June 13, 2008  
www.xilinx.com  
Product Specification  
1

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