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XAM62A74AUMHAAMB

更新时间： 2024-12-02 11:10:11
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德州仪器 - TI /
页数 文件大小 规格书
218页 4175K
描述
2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power systems, machine vision, robotics | AMB | 484 | -40 to 105

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XAM62A74AUMHAAMB 数据手册

 浏览型号XAM62A74AUMHAAMB的Datasheet PDF文件第2页浏览型号XAM62A74AUMHAAMB的Datasheet PDF文件第3页浏览型号XAM62A74AUMHAAMB的Datasheet PDF文件第4页浏览型号XAM62A74AUMHAAMB的Datasheet PDF文件第5页浏览型号XAM62A74AUMHAAMB的Datasheet PDF文件第6页浏览型号XAM62A74AUMHAAMB的Datasheet PDF文件第7页 
AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1  
SPRSP77 – MARCH 2023  
AM62Ax Sitara™ Processors  
•
One Camera Serial interface (CSI-2) Receiver with  
4-Lane D-PHY  
1 Features  
– MIPI® CSI-2 v1.3 Compliant + MIPI D-PHY 1.2  
– Support for 1,2,3 or 4 data lane mode up to 1.5  
Gbps per lane  
– ECC verification/correction with CRC check +  
ECC on RAM  
– Virtual Channel support (up to 16)  
– Ability to write stream data directly to DDR via  
DMA  
Video Encoder/Decoder  
– Support for HEVC (H.265) Main profiles at  
Level 5.1 High-tier  
– Support for H.264 BaseLine/Main/High Profiles  
at Level 5.2  
– Support for up to 4K UHD resolution  
(3840 × 2160)  
Processor Cores:  
•
Up to Quad Arm® Cortex®-A53 microprocessor  
subsystem at up to 1.4 GHz  
– Quad-core Cortex-A53 cluster with 512KB L2  
shared cache with SECDED ECC  
– Each A53 core has 32KB L1 DCache with  
SECDED ECC and 32KB L1 ICache with Parity  
protection  
•
•
Single-core Arm® Cortex®-R5F at up to 800 MHz,  
integrated as part of MCU Channel with FFI  
– 32KB ICache, 32KB L1 DCache, and 64KB  
TCM with SECDED ECC on all memories  
– 512KB SRAM with SECDED ECC  
Single-core Arm® Cortex®-R5F at up to 800 MHz,  
integrated to support Device Management  
– 32KB ICache, 32KB L1 DCache, and 64KB  
TCM with SECDED ECC on all memories  
Deep Learning Accelerator based on Single-core  
C7x  
•
•
•
Clocking options supporting 240 MPixels/s,  
120 MPixels/s, or 60 MPixels/s  
Motion JPEG encode at 416 MPixels/s with  
resolutions up to 4K UHD (3840 × 2160)  
•
Memory Subsystem:  
– C7x floating point, up to 40 GFLOPS, 256-bit  
Vector DSP at 1.0 GHz  
– Matrix Multiply Accelerator (MMA), up to 2  
TOPS (8b) at 1.0 GHz  
– 32KB L1 DCache with SECDED ECC and  
64KB L1 ICache with Parity protection  
– 1.25MB of L2 SRAM with SECDED ECC  
•
Up to 2.29MB of On-chip RAM  
– 64KB of On-Chip RAM (OCRAM) with  
SECDED ECC, can be divided into smaller  
banks in increments of 32KB for as many as  
2 separate memory banks  
– 256KB of On-Chip RAM with SECDED ECC in  
SMS Subsystem  
– 176KB of On-Chip RAM with SECDED ECC in  
SMS Subsystem for TI security firmware  
– 512KB of On-chip RAM with SECDED ECC in  
Cortex-R5F MCU Subsystem  
•
Vision Processing Accelerators (VPAC) with Image  
Signal Processor (ISP) and multiple vision assist  
accelerators:  
– 315 MPixel/s ISP; Up to 5MP @ 60 fps  
– Support for 12-bit RGB-IR  
– 64KB of On-chip RAM with SECDED ECC in  
Device/Power Manager Subsystem  
– 1.25MB of L2 SRAM with SECDED ECC in C7x  
Deep Learning Accelerator  
– Support for up to 16-bit input RAW format  
– Line support up to 4096  
– Wide Dynamic Range (WDR), Lens Distortion  
Correction (LDC), Vision Imaging Subsystem  
(VISS), and Multi-Scalar (MSC) support  
•
DDR Subsystem (DDRSS)  
– Supports LPDDR4  
•
Output color format : 8-bits, 12-bits, and  
YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL  
– 32-bit data bus with inline ECC  
– Supports speeds up to 3733 MT/s  
– Max addressable range of 8GBytes  
Multimedia:  
•
Display subsystem  
– Single display support  
– Up to 2048x1080 @ 60fps  
– Up to 165-MHz pixel clock support with  
independent PLL  
– DPI 24-bit RGB parallel interface  
– Supports safety features such as freeze frame  
detection and MISR data check  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change  
without notice.  
 
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