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XA3S400-4PQ208Q

更新时间： 2024-11-08 19:42:35
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
6页 106K
描述
Field Programmable Gate Array, 896 CLBs, 400000 Gates, 125MHz, 8064-Cell, PQFP208, PLASTIC, QFP-208

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XA3S400-4PQ208Q 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：PLASTIC, QFP-208针数：208
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.86最大时钟频率：125 MHz
JESD-30 代码：S-PQFP-G208JESD-609代码：e0
长度：28 mm湿度敏感等级：3
可配置逻辑块数量：896等效关口数量：400000
输入次数：264逻辑单元数量：8064
输出次数：264端子数量：208
最高工作温度：125 °C最低工作温度：-40 °C
组织：896 CLBS, 400000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：FQFP封装等效代码：QFP208,1.2SQ,20
封装形状：SQUARE封装形式：FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：225电源：1.2,1.2/3.3,2.5 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
筛选级别：AEC-Q100座面最大高度：4.1 mm
子类别：Field Programmable Gate Arrays最大供电电压：1.26 V
最小供电电压：1.14 V标称供电电压：1.2 V
表面贴装：YES温度等级：AUTOMOTIVE
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：28 mm
Base Number Matches：1

XA3S400-4PQ208Q 数据手册

 浏览型号XA3S400-4PQ208Q的Datasheet PDF文件第2页浏览型号XA3S400-4PQ208Q的Datasheet PDF文件第3页浏览型号XA3S400-4PQ208Q的Datasheet PDF文件第4页浏览型号XA3S400-4PQ208Q的Datasheet PDF文件第5页浏览型号XA3S400-4PQ208Q的Datasheet PDF文件第6页 
06  
Spartan-3 Automotive XA FPGA  
Family:  
Introduction and Ordering  
Advance Product Specification  
R
0
0
DS314-1 (v1.1) December 20, 2004  
-
-
-
-
-
-
622 Mb/s data transfer rate per I/O  
Introduction  
Seventeen single-ended signal standards  
Seven differential signal standards including LVDS  
Termination by Digitally Controlled Impedance  
Signal swing ranging from 1.14V to 3.45V  
Double Data Rate (DDR) support  
The Xilinx Automotive (XA) Spartan™-3 family of Field-Pro-  
grammable Gate Arrays is specifically designed to meet the  
needs of high volume, cost-sensitive automotive consumer  
electronic applications. The four-member family offers den-  
sities ranging from 50,000 to one million system gates, as  
shown in Table 1.  
•
Logic resources  
-
-
-
-
-
Abundant logic cells with shift register capability  
Wide multiplexers  
Fast look-ahead carry logic  
Dedicated 18 x 18 multipliers  
JTAG logic compatible with IEEE 1149.1/1532  
XA devices are available in both the extended-temperature  
Q-grade (-40°C to +125°C) and industrial I-grade (-40°C to  
+100°C) and are qualified to the industry-recognized  
AEC-Q100 standard.  
The XA Spartan-3 family builds on the success of the earlier  
XA Spartan-IIE family by increasing the amount of logic  
resources, the capacity of internal RAM, the total number of  
I/Os, and the overall level of performance as well as by  
improving clock management functions. Numerous  
enhancements derive from state-of-the-art Virtex™-II tech-  
nology. These Spartan-3 enhancements, combined with  
advanced process technology, deliver more functionality  
and bandwidth per dollar than was previously possible, set-  
ting new standards in the programmable logic industry.  
•
•
SelectRAM™ hierarchical memory  
-
-
Up to 432 Kbits of total block RAM  
Up to 120 Kbits of total distributed RAM  
Digital Clock Manager (up to four DCMs)  
-
-
Clock skew elimination  
Frequency synthesis  
•
•
Fully supported by Xilinx ISE development system  
Synthesis, mapping, placement and routing  
-
MicroBlaze™ processor, CAN, LIN, PCI, and other  
cores  
Because of their exceptionally low cost, Spartan-3 FPGAs  
are ideally suited to a wide range of advanced automotive  
electronics modules and systems ranging from the latest  
driver assistance and infotainment systems to reconfig-  
urable instrument clusters and ECU gateways.  
•
•
Pb-free packaging options  
Xilinx and all of our production partners are qualified to  
QS-9000, moving to TS16949 in 2005.  
•
Please refer to the Spartan-3 complete data sheet  
(DS099) for a full product description, AC and DC  
specifications, and package pinout descriptions.  
The Spartan-3 family is a superior alternative to mask pro-  
grammed ASICs. FPGAs avoid the high initial cost, the  
lengthy development cycles, and the inherent inflexibility of  
conventional ASICs. Also, FPGA programmability permits  
design upgrades in the field with no hardware replacement  
necessary, an impossibility with ASICs.  
Features  
•
AEC-Q100 device qualification and full PPAP support  
available in both extended temperature Q-grade and  
I-grade.  
•
Guaranteed to meet full electrical specification up to  
TJ=-40°C to +125°C.  
•
•
Revolutionary 90-nanometer process technology  
Very low cost, high-performance logic solution for  
high-volume, automotive applications  
-
Three power rails: for core (1.2V), I/Os (1.2V to  
3.0V), and auxiliary purposes (2.5V)  
•
SelectIO™ signaling  
Up to 333 I/O pins  
-
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS314-1 (v1.1) December 20, 2004  
www.xilinx.com  
1
Advance Product Specification  
123456

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