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XA3S1200E-4VQG100Q PDF预览

XA3S1200E-4VQG100Q

更新时间： 2024-11-28 15:58:11
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
37页 723K
描述
Field Programmable Gate Array, 2168 CLBs, 1200000 Gates, 572MHz, CMOS, PQFP100, 16 X 16 MM, LEAD FREE, VQFP-100

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XA3S1200E-4VQG100Q 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：QFP包装说明：TFQFP,
针数：100Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.82
最大时钟频率：572 MHzCLB-Max的组合延迟：4.88 ns
JESD-30 代码：S-PQFP-G100JESD-609代码：e3
长度：14 mm湿度敏感等级：3
可配置逻辑块数量：2168等效关口数量：1200000
端子数量：100最高工作温度：125 °C
最低工作温度：-40 °C组织：2168 CLBS, 1200000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：TFQFP
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压：1.26 V最小供电电压：1.14 V
标称供电电压：1.2 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

XA3S1200E-4VQG100Q 数据手册

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37  
R
XA Spartan-3E Automotive  
FPGA Family Data Sheet  
0
DS635 (v2.0) September 9, 2009  
Product Specification  
Summary  
The Xilinx® Automotive (XA) Spartan®-3E family of FPGAs  
is specifically designed to meet the needs of high-volume,  
cost-sensitive automotive electronics applications. The  
five-member family offers densities ranging from 100,000 to  
1.6 million system gates, as shown in Table 1.  
-
-
Enhanced Double Data Rate (DDR) support  
DDR SDRAM support up to 266 Mb/s  
•
Abundant, flexible logic resources  
-
Densities up to 33,192 logic cells, including  
optional shift register or distributed RAM support  
Efficient wide multiplexers, wide logic  
Fast look-ahead carry logic  
Enhanced 18 x 18 multipliers with optional pipeline  
IEEE 1149.1/1532 JTAG programming/debug port  
-
-
-
-
Introduction  
XA devices are available in both extended-temperature  
Q-Grade (–40°C to +125°C T ) and I-Grade (–40°C to  
J
+100°C T ) and are qualified to the industry recognized  
J
•
•
Hierarchical SelectRAM™ memory architecture  
-
-
AEC-Q100 standard.  
Up to 648 Kbits of fast block RAM  
Up to 231 Kbits of efficient distributed RAM  
The XA Spartan-3E family builds on the success of the ear-  
lier XA Spartan-3 family by increasing the amount of logic  
per I/O, significantly reducing the cost per logic cell. New  
features improve system performance and reduce the cost  
of configuration. These XA Spartan-3E FPGA enhance-  
ments, combined with advanced 90 nm process technology,  
deliver more functionality and bandwidth per dollar than was  
previously possible, setting new standards in the program-  
mable logic industry.  
Up to eight Digital Clock Managers (DCMs)  
-
-
-
-
Clock skew elimination (delay locked loop)  
Frequency synthesis, multiplication, division  
High-resolution phase shifting  
Wide frequency range (5 MHz to over 300 MHz)  
•
•
Eight global clocks plus eight additional clocks per  
each half of device, plus abundant low-skew routing  
Configuration interface to industry-standard PROMs  
-
-
Complete Xilinx ISE® and WebPACK™ software  
support  
MicroBlaze™ and PicoBlaze™ embedded processor  
cores  
Because of their exceptionally low cost, XA Spartan-3E  
FPGAs are ideally suited to a wide range of automotive  
applications, including infotainment, driver information, and  
driver assistance modules.  
Low-cost, space-saving SPI serial Flash PROM  
x8 or x8/x16 parallel NOR Flash PROM  
•
•
•
•
The XA Spartan-3E family is a superior alternative to mask  
programmed ASICs and ASSPs. FPGAs avoid the high ini-  
tial mask set costs and lengthy development cycles, while  
also permitting design upgrades in the field with no hard-  
ware replacement necessary because of its inherent pro-  
grammability, an impossibility with conventional ASICs and  
ASSPs with their inflexible hardware architecture.  
Fully compliant 32-/64-bit 33 MHz PCI™ technology  
support  
Low-cost QFP and BGA packaging options  
-
Common footprints support easy density migration  
Refer to Spartan-3E FPGA Family: Complete Data Sheet  
(DS312) for a full product description, AC and DC specifica-  
tions, and package pinout descriptions. Any values shown  
specifically in this XA Spartan-3E Automotive FPGA Family  
data sheet override those shown in DS312.  
Features  
•
Very low-cost, high-performance logic solution for  
high-volume automotive applications  
•
•
Proven advanced 90-nanometer process technology  
Multi-voltage, multi-standard SelectIO™ interface pins  
For information regarding reliability qualification, refer to  
RPT081 (Xilinx Spartan-3E Family Automotive Qualification  
Report) and RPT012 (Spartan-3/3E UMC-12A 90 nm Qual-  
ification Report).  
-
-
Up to 376 I/O pins or 156 differential signal pairs  
LVCMOS, LVTTL, HSTL, and SSTL single-ended  
signal standards  
-
-
-
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling  
622+ Mb/s data transfer rate per I/O  
True LVDS, RSDS, mini-LVDS, differential  
HSTL/SSTL differential I/O  
© 2007–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other  
countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.  
DS635 (v2.0) September 9, 2009  
www.xilinx.com  
Product Specification  
1
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