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XA3S1400A-4FGG400I PDF预览

XA3S1400A-4FGG400I

更新时间： 2024-11-29 19:41:11
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
57页 1856K
描述
Field Programmable Gate Array, 2816 CLBs, 1400000 Gates, 667MHz, CMOS, PBGA400, LEAD FREE, MS-034, FGBGA-400

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XA3S1400A-4FGG400I 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：BGA包装说明：LEAD FREE, MS-034, FGBGA-400
针数：400Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.82
最大时钟频率：667 MHzCLB-Max的组合延迟：4.88 ns
JESD-30 代码：S-PBGA-B400JESD-609代码：e1
长度：21 mm湿度敏感等级：3
可配置逻辑块数量：2816等效关口数量：1400000
端子数量：400组织：2816 CLBS, 1400000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：250可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：2.43 mm
最大供电电压：1.26 V最小供电电压：1.14 V
标称供电电压：1.2 V表面贴装：YES
技术：CMOS端子面层：TIN SILVER COPPER
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：21 mmBase Number Matches：1

XA3S1400A-4FGG400I 数据手册

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57  
XA Spartan-3A Automotive  
FPGA Family Data Sheet  
DS681 (v2.0) April 22, 2011  
Product Specification  
Summary  
The Xilinx Automotive (XA) Spartan®-3A family of FPGAs  
solves the design challenges in most high-volume,  
cost-sensitive, I/O-intensive automotive electronics  
applications. The four-member family offers densities  
ranging from 200,000 to 1.4 million system gates, as shown  
in Table 1.  
•
•
640+ Mb/s data transfer rate per differential I/O  
LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O  
with integrated differential termination resistors  
Enhanced Double Data Rate (DDR) support  
DDR/DDR2 SDRAM support up to 266 Mb/s  
Fully compliant 32-/64-bit, 33 MHz PCI™ technology  
support  
•
•
•
Introduction  
•
Abundant, flexible logic resources  
•
Densities up to 25,344 logic cells, including optional shift  
register or distributed RAM support  
XA devices are available in both extended-temperature  
Q-Grade (–40°C to +125°C T ) and I-Grade (–40°C to  
J
+100°C T ) and are qualified to the industry recognized  
AEC-Q100 standard.  
•
•
•
•
Efficient wide multiplexers, wide logic  
Fast look-ahead carry logic  
Enhanced 18 x 18 multipliers with optional pipeline  
IEEE 1149.1/1532 JTAG programming/debug port  
J
The XA Spartan-3A family builds on the success of the  
earlier XA Spartan-3E and XA Spartan-3 FPGA families by  
increasing the amount of I/O per logic, significantly reducing  
the cost per I/O. New features improve system performance  
and reduce the cost of configuration. These XA Spartan-3A  
family enhancements, combined with proven 90 nm process  
technology, deliver more functionality and bandwidth per  
dollar than ever before, setting the new standard in the  
programmable logic industry.  
•
•
Hierarchical SelectRAM™ memory architecture  
•
Up to 576 Kbits of fast block RAM with byte write enables  
for processor applications  
Up to 176 Kbits of efficient distributed RAM  
•
Up to eight Digital Clock Managers (DCMs)  
•
•
•
•
Clock skew elimination (delay locked loop)  
Frequency synthesis, multiplication, division  
High-resolution phase shifting  
Because of their exceptionally low cost, XA Spartan-3A  
FPGAs are ideally suited to a wide range of automotive  
electronics applications, including infotainment, driver  
information, and driver assistance modules.  
Wide frequency range (5 MHz to over 320 MHz)  
•
•
Eight low-skew global clock networks, eight additional  
clocks per half device, plus abundant low-skew routing  
The XA Spartan-3A family is a superior alternative to mask  
programmed ASICs. FPGAs avoid the high initial mask set  
costs and lengthy development cycles, while also permitting  
design upgrades in the field with no hardware replacement  
necessary because of its inherent programmability, an  
impossibility with conventional ASICs and ASSPs with their  
inflexible architecture.  
Configuration interface to industry-standard PROMs  
•
•
•
Low-cost, space-saving SPI serial Flash PROM  
x8 or x8/x16 parallel NOR Flash PROM  
Unique Device DNA identifier for design authentication  
•
•
•
Complete Xilinx ISE® and WebPACK™ software  
support plus Spartan-3A Starter Kit  
MicroBlaze™ and PicoBlazeembedded processor  
cores  
Features  
BGA packaging, Pb-free ONLY  
•
•
Very low cost, high-performance logic solution for  
Common footprints support easy density migration  
high-volume, cost-conscious applications  
Refer to the Spartan-3A FPGA Family Data Sheet (DS529)  
for a full product description, AC and DC specifications, and  
package pinout descriptions. Any values shown specifically  
in this XA Spartan-3A Automotive FPGA Family data sheet  
override those shown in DS529.  
•
•
•
Dual-range V  
supply simplifies 3.3V-only design  
CCAUX  
Suspend, Hibernate modes reduce system power  
Multi-voltage, multi-standard SelectIO™ interface pins  
•
•
•
•
•
•
Up to 375 I/O pins or 165 differential signal pairs  
LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O  
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling  
Selectable output drive, up to 24 mA per pin  
QUIETIO standard reduces I/O switching noise  
Full 3.3V 10% compatibility and hot swap compliance  
For information regarding reliability qualification, refer to  
RPT103 (Xilinx Spartan-3A Family Automotive Qualification  
Report) and RPT070 (Spartan-3A Commercial Qualification  
Report).  
© Copyright 2008–2011 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the  
United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.  
DS681 (v2.0) April 22, 2011  
www.xilinx.com  
Product Specification  
1
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