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X9252YV24I-2.7 PDF预览

X9252YV24I-2.7

更新时间： 2024-02-07 10:22:30
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
19页 386K
描述
Low Power + Quad 256-Tap + 2-Wire Bus + Up/Down Interface

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X9252YV24I-2.7 技术参数

生命周期：TransferredReach Compliance Code：unknown
风险等级：5.67Is Samacsys：N
Base Number Matches：1

X9252YV24I-2.7 数据手册

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X9252  
®
Low Power + Quad 256-tap + 2-Wire Bus + Up/Down Interface  
Data Sheet  
September 14, 2005  
FN8167.1  
Quad Digitally-Controlled (XDCP™)  
Potentiometer  
Features  
• Quad Solid State Potentiometer  
The X9252 integrates 4 digitally controlled potentiometers  
(XDCP) on a monolithic CMOS integrated circuit.  
• 256 Wiper Tap Points-0.4% Resolution  
• 2-Wire Serial Interface for Write, Read, and Transfer  
Operations of the Potentiometer  
The digitally controlled potentiometers are implemented  
using 255 resistive elements in a series array. Between each  
pair of elements are tap points connected to wiper terminals  
through switches. The position of each wiper on the array is  
controlled by the user through the Up/Down (U/D) or 2-wire  
bus interface. The wiper of each potentiometer has an  
associated volatile Wiper Counter Register (WCR) and four  
non-volatile Data Registers (DRs) that can be directly written  
to and read by the user. The contents of the WCR controls  
the position of the wiper on the resistor array through the  
switches. At power-up, the device recalls the contents of the  
default data registers DR00, DR10, DR20, DR30, to the  
corresponding WCR.  
• Up/Down Interface for Individual Potentiometers  
• Wiper Resistance: 40Ω Typical  
• Non-Volatile Storage of Wiper Positions  
• Power On Recall. Loads Saved Wiper Position on Power-  
Up.  
• Standby Current < 20µA Max  
• Maximum Wiper Current: 3mA  
• V : 2.7V to 5.5V Operation  
CC  
• 2.8kΩ,10kΩ, 50kΩ, 100kΩ Version of Total Pot Resistance  
• Endurance: 100, 000 Data Changes per Bit per Register  
• 100 yr. Data Retention  
Each DCP can be used as a three-terminal potentiometer or  
as a two terminal variable resistor in a wide variety of  
applications including the programming of bias voltages, the  
implementation of ladder networks, and three resistor  
programmable networks.  
• 24 Ld TSSOP  
• Pb-Free Plus Anneal Available (RoHS Compliant)  
Pinout  
X9252  
(24 LD TSSOP)  
TOP VIEW  
24  
23  
22  
DS1  
SCL  
DS0  
A0  
1
2
3
4
5
6
R
R
L2  
W3  
21  
20  
19  
18  
17  
16  
R
R
H2  
H3  
R
R
W2  
L3  
CS  
U/D  
X9252  
V
V
SS  
CC  
7
8
R
R
W1  
L0  
9
R
R
H1  
H0  
10  
R
R
L1  
W0  
15  
14  
13  
A1  
11  
12  
A2  
SDA  
WP  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved  
All other trademarks mentioned are the property of their respective owners.  
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X9252YV24I-2.7 替代型号

型号 品牌 替代类型 描述 数据表
X9252YV24IZ-2.7 INTERSIL

完全替代

 Low Power + Quad 256-Tap + 2-Wire Bus + Up/Down Interface

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