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X5168V14-2.7AT1 PDF预览

X5168V14-2.7AT1

更新时间： 2024-11-07 21:11:11
品牌 Logo 应用领域
瑞萨 - RENESAS 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
页数 文件大小 规格书
19页 363K
描述
IC,SERIAL EEPROM,2KX8,CMOS,TSSOP,14PIN,PLASTIC

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X5168V14-2.7AT1 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete包装说明：TSSOP, TSSOP14,.25
Reach Compliance Code：not_compliant风险等级：5.82
数据保留时间-最小值：100耐久性：100000 Write/Erase Cycles
JESD-30 代码：R-PDSO-G14JESD-609代码：e0
内存密度：16384 bit内存集成电路类型：EEPROM
内存宽度：8端子数量：14
字数：2048 words字数代码：2000
最高工作温度：70 °C最低工作温度：
组织：2KX8封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP14,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行：SERIAL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3/5 V认证状态：Not Qualified
串行总线类型：SPI最大待机电流：0.000001 A
子类别：EEPROMs最大压摆率：0.005 mA
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
写保护：HARDWARE/SOFTWAREBase Number Matches：1

X5168V14-2.7AT1 数据手册

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X5168, X5169  
®
(Replaces X25268, X25169)  
Data Sheet  
September 16, 2005  
FN8130.1  
CPU Supervisor with 16Kbit SPI EEPROM  
Features  
• Low VCC Detection and Reset Assertion  
- Five standard reset threshold voltages  
- Re-program low VCC reset threshold voltage using  
special programming sequence  
These devices combine three popular functions, Power-on  
Reset Control, Supply Voltage Supervision, and Block Lock  
Protect Serial EEPROM Memory in one package. This  
combination lowers system cost, reduces board space  
requirements, and increases reliability.  
- Reset signal valid to VCC = 1V  
Applying power to the device activates the power-on reset  
circuit which holds RESET/RESET active for a period of  
time. This allows the power supply and oscillator to stabilize  
before the processor can execute code.  
• Long Battery Life with Low Power Consumption  
- <50µA max standby current, watchdog on  
- <1µA max standby current, watchdog off  
- <400µA max active current during read  
The device’s low VCC detection circuitry protects the user’s  
system from low voltage conditions by holding  
• 16Kbits of EEPROM  
• Built-in Inadvertent Write Protection  
RESET/RESET active when VCC falls below a minimum VCC  
trip point. RESET/RESET remains asserted until VCC returns  
to proper operating level and stabilizes. Five industry  
standard VTRIP thresholds are available, however, Intersil’s  
unique circuits allow the threshold to be reprogrammed to  
meet custom requirements or to fine-tune the threshold in  
applications requiring higher precision.  
- Power-up/power-down protection circuitry  
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block  
Lock™ protection  
- In circuit programmable ROM mode  
• 2MHz SPI Interface Modes (0,0 & 1,1)  
• Minimize EEPROM Programming Time  
- 32-byte page write mode  
- Self-timed write cycle  
- 5ms write cycle time (typical)  
• 2.7V to 5.5V and 4.5V to 5.5V Power Supply  
Operation  
• Available Packages  
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP  
• Pb-Free Plus Anneal Available (RoHS Compliant)  
Block Diagram  
WP  
Protect Logic  
SI  
Data  
Register  
Status  
Register  
SO  
Command  
Decode &  
Control  
SCK  
CS  
4Kbits  
4Kbits  
Logic  
8Kbits  
Reset  
Timebase  
RESET/RESET  
Power-on and  
Low Voltage  
Reset  
V
+
-
CC  
Generation  
X5168 = RESET  
X5169 = RESET  
V
TRIP  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2005. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
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