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X4325S8Z-2.7A PDF预览

X4325S8Z-2.7A

更新时间： 2024-11-01 15:58:07
品牌 Logo 应用领域
瑞萨 - RENESAS 光电二极管
页数 文件大小 规格书
22页 342K
描述
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8

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X4325S8Z-2.7A 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP,
针数：8Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.69其他特性：RESET THRESHOLD VOLTAGE IS 2.92V
可调阈值：YES模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9022 mm信道数量：1
功能数量：1端子数量：8
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.7272 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9116 mmBase Number Matches：1

X4325S8Z-2.7A 数据手册

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X4323, X4325  
®
32k, 4k x 8 Bit  
Data Sheet  
May 25, 2006  
FN8122.1  
DESCRIPTION  
CPU Supervisor with 32k EEPROM  
The X4323, X4325 combines four popular functions,  
Power-on Reset Control, Watchdog Timer, Supply Volt-  
age Supervision, and Serial EEPROM Memory in one  
package. This combination lowers system cost,  
reduces board space requirements, and increases  
reliability.  
FEATURES  
• Selectable watchdog timer  
• Low V detection and reset assertion  
CC  
—Four standard reset threshold voltages  
—Adjust low V reset threshold voltage using  
CC  
special programming sequence  
Applying power to the device activates the power-on  
reset circuit which holds RESET/RESET active for a  
period of time. This allows the power supply and oscilla-  
tor to stabilize before the processor can execute code.  
—Reset signal valid to V = 1V  
CC  
• Low power CMOS  
—<20µA max standby current, watchdog on  
—<1µA standby current, watchdog off  
—3mA active current  
• 32Kbits of EEPROM  
—64-byte page write mode  
The Watchdog Timer provides an independent protec-  
tion mechanism for microcontrollers. When the micro-  
controller fails to restart a timer within a selectable time  
out interval, the device activates the RESET/RESET  
signal. The user selects the interval from three preset  
values. Once selected, the interval does not change,  
even after cycling the power.  
—Self-timed write cycle  
—5ms write cycle time (typical)  
• Built-in inadvertent write protection  
—Power-up/power-down protection circuitry  
—Block Lock (1, 2, 4, 8 pages, all, none)  
• 400kHz 2-wire interface  
• 2.7V to 5.5V power supply operation  
• Available packages  
—8 Ld SOIC  
The device’s low V  
detection circuitry protects the  
CC  
user’s system from low voltage conditions, resetting the  
system when V falls below the set minimum V trip  
CC  
CC  
point. RESET/RESET is asserted until V  
returns to  
CC  
proper operating level and stabilizes. Four industry  
standard V thresholds are available, however, Inter-  
—8 Ld TSSOP  
• Pb-free plus anneal available (RoHS compliant)  
TRIP  
sil’s unique circuits allow the threshold to be repro-  
grammed to meet custom requirements or to fine-tune  
the threshold for applications requiring higher precision.  
BLOCK DIAGRAM  
Watchdog Transition  
Detector  
Watchdog  
Timer Reset  
WP  
Protect Logic  
RESET (X4323)  
RESET (X4325)  
Data  
Register  
SDA  
Status  
Register  
EEPROM Array  
Command  
Reset &  
Watchdog  
Timebase  
SCL  
Decode &  
Control  
Logic  
S0  
S1  
VCC Threshold  
Reset logic  
Power-on and  
+
-
Low Voltage  
VCC  
Reset  
Generation  
VTRIP  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
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