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X25650Z-2.5 PDF预览

X25650Z-2.5

更新时间: 2024-01-24 07:14:03
品牌 Logo 应用领域
其他 - ETC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
15页 214K
描述
SPI Serial EEPROM

X25650Z-2.5 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:XBGA-8Reach Compliance Code:unknown
风险等级:5.88其他特性:1 MILLION ENDURANCE CYCLES; 100 YEARS DATA RETENTION
最大时钟频率 (fCLK):5 MHz数据保留时间-最小值:100
耐久性:100000 Write/Erase CyclesJESD-30 代码:R-PBGA-B8
JESD-609代码:e0长度:4.048 mm
内存密度:65536 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:8字数:8192 words
字数代码:8000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX8封装主体材料:PLASTIC/EPOXY
封装代码:VBGA封装等效代码:BGA8,2X4,48/40
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE
并行/串行:SERIAL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/5 V认证状态:Not Qualified
座面最大高度:0.675 mm串行总线类型:SPI
最大待机电流:0.000001 A子类别:EEPROMs
最大压摆率:0.005 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.5 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:2.118 mm最长写入周期时间 (tWC):10 ms
写保护:HARDWARE/SOFTWAREBase Number Matches:1

X25650Z-2.5 数据手册

 浏览型号X25650Z-2.5的Datasheet PDF文件第2页浏览型号X25650Z-2.5的Datasheet PDF文件第3页浏览型号X25650Z-2.5的Datasheet PDF文件第4页浏览型号X25650Z-2.5的Datasheet PDF文件第5页浏览型号X25650Z-2.5的Datasheet PDF文件第6页浏览型号X25650Z-2.5的Datasheet PDF文件第7页 
Recommended System Management  
Alternative: X5643  
64K  
8K x 8 Bit  
X25650  
5MHz SPI Serial EEPROM with Block LockProtection  
FEATURES  
• Packages  
—8-lead SOIC  
—14-lead SOIC  
• 5MHz clock rate  
• Low Power CMOS  
—<1µA standby current  
—<5mA active current  
DESCRIPTION  
• 2.5V To 5.5V power supply  
• SPI modes (0,0 & 1,1)  
• 8K X 8 bits  
—32 byte page mode  
• Block lock protection  
—Protect 1/4, 1/2 or all of EEPROM array  
• Programmable hardware write protection  
—In-circuit programmable ROM mode  
• Built-in inadvertent write protection  
Power-up/down protection circuitry  
—Write enable latch  
The X25650 is a CMOS 65,536-bit serial EEPROM,  
internally organized as 8K x 8. The X25650 features a  
Serial Peripheral Interface (SPI) and software protocol,  
allowing operation on a simple three-wire bus. The bus  
signals are a clock input (SCK) plus separate data in  
(SI) and data out (SO) lines. Access to the device is  
controlled through a chip select (CS) input, allowing  
any number of devices to share the same bus.  
The X25650 also features two additional inputs that pro-  
vide the end user with added flexibility. By asserting the  
HOLD input, the X25650 will ignore transitions on its  
inputs, thus allowing the host to service higher priority  
interrupts. The WP input can be used as a hardwire input  
to the X25650 disabling all write attempts to the status  
register, thus providing a mechanism for limiting end user  
capability of altering 0, 1/4, 1/2 or all of the memory.  
—Write protect pin  
• Self-timed write cycle  
—5ms write cycle time (typical)  
• High reliability  
—Endurance: 1,000,000 cycles  
—Data retention: 100 years  
—ESD protection: 2000V on all pins  
The X25650 utilizes Xicor’s proprietary Direct Write™  
cell, providing a minimum endurance of 1,000,000  
cycles and a minimum data retention of 100 years.  
BLOCK DIAGRAM  
Write  
Protect  
Logic  
Status  
Register  
X Decode  
Logic  
8Kbyte  
Array  
64  
64  
64 X 256  
64 X 256  
SO  
SI  
Command  
Decode  
and  
Control  
Logic  
SCK  
CS  
HOLD  
128  
128 X 256  
Write  
Control  
and  
32  
8
WP  
Timing  
Logic  
Y Decode  
Data Register  
Direct Writeand Block LockProtection is a trademark of Xicor, Inc.  
REV 1.1 9/8/00  
Characteristics subject to change without notice. 1 of 15  
www.xicor.com  
This Material Copyrighted by Its Respective Manufacturer  

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