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X24645AM PDF预览

X24645AM

更新时间: 2024-02-15 01:08:50
品牌 Logo 应用领域
XICOR 可编程只读存储器
页数 文件大小 规格书
18页 86K
描述
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X24645AM 数据手册

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64K  
8192 x 8 Bit  
X24645  
2
Advanced 2-Wire Serial E PROM with Block LockTM Protection  
FEATURES  
DESCRIPTION  
2
2.7V to 5.5V Power Supply  
The X24645 is a CMOS 65,536-bit serial E PROM,  
internally organized 8192 x 8. The X24645 features a  
serial interface and software protocol allowing opera-  
tion on a simple two wire bus.  
Low Power CMOS  
—Active Read Current Less Than 1mA  
—Active Write Current Less Than 3mA  
—Standby Current Less Than 1µA  
Internally Organized 8192 x 8  
New Programmable Block Lock Protection  
—Software Write Protection  
Two device select inputs (S , S ) allow up to four  
1
2
devices to share a common two wire bus.  
A Write Protect Register at the highest address loca-  
tion, 1FFFh, provides three new write protection  
features: Software Write Protect, Block Write Protect,  
and Hardware Write Protect. The Software Write  
Protect feature prevents any nonvolatile writes to the  
X24645 until the WEL bit in the write protect register is  
set. The Block Write Protection feature allows the user  
to individually write protect four blocks of the array by  
programming two bits in the write protect register. The  
Programmable Hardware Write Protect feature allows  
—Programmable hardware Write Protect  
2
Block Lock (0, 1/4, 1/2, or all of the E PROM  
array)  
2 Wire Serial Interface  
Bidirectional Data Transfer Protocol  
32 Byte Page Write Mode  
—Minimizes Total Write Time Per Byte  
Self Timed Write Cycle  
—Typical Write Cycle Time of 5ms  
High Reliability  
the user to install the X24645 with WP tied to V  
,
CC  
—Endurance: 100,000 Cycles  
—Data Retention: 100 Years  
Available Packages  
program the entire memory array in place, and then  
enable the hardware write protection by programming  
a WPEN bit in the write protect register. After this,  
selected blocks of the array, including the write protect  
register itself, are permanently write protected, as long  
as WP remains HIGH.  
—8-Lead PDIP  
—8-Lead SOIC (JEDEC)  
—14-Lead SOIC (JEDEC)  
—20-Lead TSSOP  
FUNCTIONAL DIAGRAM  
WP  
H.V. GENERATION  
START CYCLE  
TIMING &  
CONTROL  
V
V
CC  
SS  
WRITE PROTECT  
REGISTER AND  
LOGIC  
START  
STOP  
SDA  
LOGIC  
CONTROL  
LOGIC  
SLAVE ADDRESS  
REGISTER  
+COMPARATOR  
2
E PROM  
256 X 256  
XDEC  
LOAD  
WORD  
INC  
SCL  
ADDRESS  
COUNTER  
S
S
2
1
R/W  
YDEC  
8
CK  
D
OUT  
PIN  
DATA REGISTER  
D
OUT  
ACK  
2783 ILL F01  
Xicor, 1995, 1996 Patents Pending  
2783-3.5 5/13/96 T1/C0/D0 NS  
Characteristics subject to change without notice  
1

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