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X1242V8I-2.7 PDF预览

X1242V8I-2.7

更新时间: 2024-02-03 06:15:59
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟光电二极管外围集成电路
页数 文件大小 规格书
24页 148K
描述
0 TIMER(S), REAL TIME CLOCK, PDSO8, PLASTIC, TSSOP-8

X1242V8I-2.7 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:PLASTIC, TSSOP-8
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.75Is Samacsys:N
最大时钟频率:0.032 MHz信息访问方法:SERIAL, 2-WIRE/I2C
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.4 mm端子数量:8
计时器数量:最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压:3.6 V最小供电电压:2.7 V
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
uPs/uCs/外围集成电路类型:TIMER, REAL TIME CLOCKBase Number Matches:1

X1242V8I-2.7 数据手册

 浏览型号X1242V8I-2.7的Datasheet PDF文件第6页浏览型号X1242V8I-2.7的Datasheet PDF文件第7页浏览型号X1242V8I-2.7的Datasheet PDF文件第8页浏览型号X1242V8I-2.7的Datasheet PDF文件第10页浏览型号X1242V8I-2.7的Datasheet PDF文件第11页浏览型号X1242V8I-2.7的Datasheet PDF文件第12页 
X1242 – Preliminary Information  
Figure 9. Sample V  
Reset Circuit  
TRIP  
V
P
4.7K  
Adjust  
Run  
µC  
RESET  
1
2
3
4
8
7
6
5
X1242  
8-L SOIC  
V
TRIP  
Adj.  
SCL  
SDA  
SERIAL COMMUNICATION  
Interface Conventions  
transfers, and provides the clock for both transmit and  
receive operations. Therefore, the devices in this fam-  
ily operate as slaves in all applications.  
The device supports a bidirectional bus oriented proto-  
col. The protocol defines any device that sends data  
onto the bus as a transmitter, and the receiving device  
as the receiver. The device controlling the transfer is  
called the master and the device being controlled is  
called the slave. The master always initiates data  
Clock and Data  
Data states on the SDA line can change only during  
SCL LOW. SDA state changes during SCL HIGH are  
reserved for indicating start and stop conditions. See  
Figure 10.  
Figure 10. Valid Data Changes on the SDA Bus  
SCL  
SDA  
Data Stable  
Data Change  
Data Stable  
Start Condition  
the device into the Standby power mode after a read  
sequence. A stop condition can only be issued by the  
master after the slave device has released the bus. See  
Figure 11.  
All commands are preceded by the start condition,  
which is a HIGH to LOW transition of SDA when SCL  
is HIGH. The device continuously monitors the SDA  
and SCL lines for the start condition and will not  
respond to any command until this condition has been  
met. See Figure 11.  
Acknowledge  
Acknowledge is a software convention used to indicate  
successful data transfer. The transmitting device,  
either master or slave, will release the bus after trans-  
mitting eight bits. During the ninth clock cycle, the  
receiver will pull the SDA line LOW to acknowledge  
that it received the eight bits of data. Refer to Figure 12.  
Stop Condition  
All communications must be terminated by a stop con-  
dition, which is a LOW to HIGH transition of SDA when  
SCL is HIGH. The stop condition is also used to place  
Characteristics subject to change without notice. 9 of 24  
REV 1.1.7 5/31/01  
www.xicor.com  

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