Datasheet > X1243

X1243

更新时间： 2022-11-27 07:37:05

品牌	Logo	应用领域
XICOR		闹钟可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数	文件大小	规格书
18页	94K
描述
Real Time Clock/Calendar/Alarm with EEPROM

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X1243 数据手册

16K

2-Wire RTC

X1243

Real Time Clock/Calendar/Alarm with EEPROM

DESCRIPTION

FEATURES

• 2 Alarms—Interrupt Output

—Settable on the Second, 10s of Seconds,

Minute, 10s of Minutes, Hour, Day, Month, or

Day of the Week

The X1243 is a Real Time Clock with clock/calendar

circuits and two alarms. The dual port clock and alarm

registers allow the clock to operate, without loss of

accuracy, even during read and write operations.

—Repeat alarm for time base generation

• 2 Wire Interface interoperable with I²C.

—400kHz data transfer rate

• Secondary Power Supply Input with internal

switch-over circuitry.

• Year 2000 Compliant

• 2K bytes of EEPROM

—64 Byte Page Write Mode

The clock/calendar provides functionality that is con-

trollable and readable through a set of registers. The

clock, using a low cost 32.768kHz crystal input, accu-

rately tracks the time in seconds, minutes, hours, date,

day, month and years. It has leap year correction,

automatic adjustment for the year 2000 and months

with less than 31 days.

—3 bit Block Lock

• Low Power CMOS

—<1µA Operating Current

An alarm match of the RTC sets an interrupt flag and

activates an interrupt pin. An alternative alarm function

provides a pulsed interrupt for long time constant time-

bases.

—<3mA Active Current during Program

—<400µA Active Current during Data Read

• Single Byte Write Capability

• Typical Nonvolatile Write Cycle Time: 5ms

• High Reliability

—100,000 Endurance Cycles

—Guaranteed Data Retention: 100 Years

• Small Package Options

The device offers a backup power input pin. This

Vback pin allows the device to be backed up by a non-

rechargeable battery. The RTC is fully operational

from 1.8 to 5.5 volts.

The X1243 provides a 2K byte EEPROM array, giving

a safe, secure memory for critical user and configura-

tion data. This memory is unaffected by complete fail-

ure of the main and backup supplies.

—8-Lead SOIC Package, 8L TSSOP Package

BLOCK DIAGRAM

Timer

Calendar

Logic

Frequency

Divider

1Hz

Time

Keeping

Registers

32.768kHz

Oscillator

(SRAM)

Control

Status

Control

Decode

Logic

Compare

Registers

Alarm

Serial

Interface

Decoder

(EEPROM)

(SRAM)

SCL

SDA

Alarm Regs

(EEPROM)

16K

EEPROM

Array

Interrupt Enable

Alarm

IRQ

Xicor, Inc. 1994, 1995, 1996 Patents Pending

9900-3003.1 4/1/99

Characteristics subject to change without notice

12 3 4 5 6 7...18

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