Datasheet > X1242V8I-2.7

X1242V8I-2.7

更新时间： 2024-02-01 19:23:58

品牌	Logo	应用领域
瑞萨 - RENESAS		时钟光电二极管外围集成电路
页数	文件大小	规格书
24页	148K
描述
0 TIMER(S), REAL TIME CLOCK, PDSO8, PLASTIC, TSSOP-8

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技术参数
数据手册

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X1242V8I-2.7 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	PLASTIC, TSSOP-8
针数：	8	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.75	Is Samacsys：	N
最大时钟频率：	0.032 MHz	信息访问方法：	SERIAL, 2-WIRE/I2C
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e0
长度：	4.4 mm	端子数量：	8
计时器数量：		最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	240
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大供电电压：	3.6 V	最小供电电压：	2.7 V
标称供电电压：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	3 mm
uPs/uCs/外围集成电路类型：	TIMER, REAL TIME CLOCK	Base Number Matches：	1

X1242V8I-2.7 数据手册

X1242 – Preliminary Information

Figure 3. Block Protect Bits

Protected Addresses

sequence is not completed for any reason (by send-

ing an incorrect number of bits or sending a start

instead of a stop, for example) the RWEL bit is not

reset and the device remains in an active mode. See

Figure 13. Use the following sequence.

X1242

Array Lock

None

600 - 7FF

Upper 1/4

Upper 1/2

Full Array

First Page

First 2 pgs

First 4 pgs

First 8 pgs

start AE ack 3F ack 02 ack stop

Followed by

400 - 7FF

000 - 7FF

start AE ack 3F ack 06 ack stop

000 - 03F

– The RWEL and WEL bits can be reset by writing a 0

to the Status Register.

000 - 07F

000 - 0FF

– A read operation occurring between any of the previ-

ous operations will not interrupt the register write

operation.

000 - 1FF

Watchdog Timer Control Bits

POWER ON RESET

The bits WD1 and WD0 control the period of the

Watchdog Timer. See Table 4 for options.

Application of power to the X1242 activates a Power

On Reset Circuit that pulls the RESET pin active. This

signal provides several beneﬁts.

Figure 4. Watchdog Timer Time Out Options

WD1 WD0

Watchdog Time Out Period

1.75 seconds

– It prevents the system microprocessor from starting

to operate with insufﬁcient voltage.

– It prevents the processor from operating prior to sta-

bilization of the oscillator.

750 milliseconds

250 milliseconds

disabled

– It allows time for an FPGA to download its conﬁgura-

tion prior to initialization of the circuit.

– It prevents communication to the EEPROM, greatly

reducing the likelihood of data corruption on power

up.

WRITING TO THE CLOCK/CONTROL REGISTERS

Changing any of the nonvolatile bits of the clock/con-

trol register requires the following steps:

When V

exceeds the device V

threshold value

TRIP

for 250ms the circuit releases RESET, allowing the

system to begin operation.

– Write a 02H to the Status Register to set the Write

Enable Latch (WEL). This is a volatile operation, so

there is no delay after the write. (Operation pre-

ceeded by a start and ended with a stop).

WATCHDOG TIMER OPERATION

– Write a 06H to the Status Register to set both the

bit.This is also a volatile cycle.The zeros in the data

byte are required. (Operation preceeded by a start

and ended with a stop).

The watchdog timer is selectable. By writing a value to

WD1 and WD0, the watchdog timer can be set to 3 dif-

ferent time out periods or off. When the Watchdog

timer is set to off, the watchdog circuit is conﬁgured for

low power operation.

– Write one to 8 bytes to the Clock/Control Registers

with the desired clock, alarm, or control data. This

sequence starts with a start bit, requires a slave byte

of “11011110” and an address within the CCR and is

terminated by a stop bit. A write to the CCR changes

EEPROM values so these initiate a nonvolatile write

cycle and will take up to 10ms to complete.Writes to

undeﬁned areas have no effect. The RWEL bit is

reset by the completion of a nonvolatile write write

cycle, so the sequence must be repeated to again

initiate another change to the CCR contents. If the

Watchdog Timer Restart

The Watchdog Timer is restarted by a falling edge of

SDA when the SCL line is high. This is also referred to

as start condition. The restart signal restarts the

watchdog timer counter, resetting the period of the

counter back to the maximum. If another start fails to

be detected prior to the watchdog timer expiration,

then the reset pin becomes active. In the event that the

restart signal occurs during a reset time out period, the

restart will have no effect.

Characteristics subject to change without notice. 6 of 24

REV 1.1.7 5/31/01

www.xicor.com

1...3 4 567 8 9...24

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与X1242V8I-2.7相关器件

型号	品牌	描述	获取价格	数据表
X1242V8I-2.7A	RENESAS	0 TIMER(S), REAL TIME CLOCK, PDSO8, PLASTIC, TSSOP-8	获取价格
X1242V8I-4.5A	RENESAS	0 TIMER(S), REAL TIME CLOCK, PDSO8, PLASTIC, TSSOP-8	获取价格
X1243	XICOR	Real Time Clock/Calendar/Alarm with EEPROM	获取价格
X1243	INTERSIL	Real Time Clock/Calendar/Alarm with EEPROM	获取价格
X1243S8	XICOR	Real Time Clock/Calendar/Alarm with EEPROM	获取价格
X1243S8	INTERSIL	Real Time Clock/Calendar/Alarm with EEPROM	获取价格

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