WS1M8-XXX
White Electronic Designs
2x512Kx8 DUALITHIC™ SRAM
FEATURES
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Access Times 17, 20, 25, 35, 45, 55ns
Revolutionary, Center Power/Ground Pinout
Packaging:
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Organized as two banks of 512Kx8
Commercial, Industrial and Military Temperature Ranges
5 Volt Power Supply
Low Power CMOS
TTL Compatible Inputs and Outputs
• 32 pin, Hermetic Ceramic DIP (Package 300)
• 36 lead Ceramic SOJ (Package 100)
• 36 lead Ceramic Flatpack (Package 226)
PIN CONFIGURATION FOR WS1M8-XDJX
AND WS1M8-XFX
PIN CONFIGURATION FOR WS1M8-XCX
36 CSOJ
32 DIP
TOP VIEW
36 FLATPACK
TOP VIEW
A18
A16
A14
A12
A7
1
2
3
4
5
6
32
VCC
A0
A1
A2
A3
A4
CS1#
I/O0
I/O1
1
2
3
4
5
6
7
8
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
31 A15
30 A17
29 WE#
28 A13
27 A8
A18
A17
A16
A15
OE#
I/O7
I/O6
GND
A6
A5
7
26 A9
A4
A3
A2
A1
8
9
25 A11
24 CS2#
23 A10
22 CS1#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
V
CC
9
GND
I/O2
I/O3
WE#
A5
A6
A7
A8
A9
10
11
12
13
14
15
16
17
18
VCC
10
11
12
13
14
15
16
I/O5
I/O4
A14
A13
A12
A11
A0
I/O0
I/O1
I/O2
GND
A10
CS2#
Pin Description
Pin Description
A0-18
I/O0-7
CS1-2#
OE#
Address Inputs
A0-18
I/O0-7
Address Inputs
Data Input/Output
Chip Selects
Output Enable
Write Enable
+5.0V Power
Ground
Data Input/Output
CS1-2#
WE#
VCC
Chip Selects
Write Enable
+5.0V Power
Ground
WE#
VCC
GND
GND
Block Diagram
Block Diagram
I/O0-7
I/O0-7
WE#
OE#
A0-18
WE#
A0-18
512K x 8
512K x 8
512K x 8
512K x 8
CS1# (1)
CS2# (1)
CS1# (1)
CS2# (1)
NOTE:
1. CS1# and CS2# are used to select the lower and upper 512Kx8 of the device. CS1# and CS2# must not be enabled at the same time.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2004
Rev. 5
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com