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WS1M8-45DJMA PDF预览

WS1M8-45DJMA

更新时间: 2024-02-07 10:24:12
品牌 Logo 应用领域
WEDC 存储内存集成电路静态存储器输出元件输入元件
页数 文件大小 规格书
6页 362K
描述
2x512Kx8 DUALITHICTM SRAM

WS1M8-45DJMA 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:CERAMIC, DFP-36Reach Compliance Code:unknown
风险等级:5.7Is Samacsys:N
最长访问时间:45 nsJESD-30 代码:R-CDFP-F36
JESD-609代码:e0长度:23.37 mm
内存密度:8388608 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:36字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:1MX8封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:GDFP封装形状:RECTANGULAR
封装形式:FLATPACK, GUARD RING并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:3.18 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:12.95 mmBase Number Matches:1

WS1M8-45DJMA 数据手册

 浏览型号WS1M8-45DJMA的Datasheet PDF文件第2页浏览型号WS1M8-45DJMA的Datasheet PDF文件第3页浏览型号WS1M8-45DJMA的Datasheet PDF文件第4页浏览型号WS1M8-45DJMA的Datasheet PDF文件第5页浏览型号WS1M8-45DJMA的Datasheet PDF文件第6页 
WS1M8-XXX  
White Electronic Designs  
2x512Kx8 DUALITHIC™ SRAM  
FEATURES  
Access Times 17, 20, 25, 35, 45, 55ns  
Revolutionary, Center Power/Ground Pinout  
Packaging:  
Organized as two banks of 512Kx8  
Commercial, Industrial and Military Temperature Ranges  
5 Volt Power Supply  
Low Power CMOS  
TTL Compatible Inputs and Outputs  
• 32 pin, Hermetic Ceramic DIP (Package 300)  
• 36 lead Ceramic SOJ (Package 100)  
• 36 lead Ceramic Flatpack (Package 226)  
PIN CONFIGURATION FOR WS1M8-XDJX  
AND WS1M8-XFX  
PIN CONFIGURATION FOR WS1M8-XCX  
36 CSOJ  
32 DIP  
TOP VIEW  
36 FLATPACK  
TOP VIEW  
A18  
A16  
A14  
A12  
A7  
1
2
3
4
5
6
32  
VCC  
A0  
A1  
A2  
A3  
A4  
CS1#  
I/O0  
I/O1  
1
2
3
4
5
6
7
8
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
NC  
31 A15  
30 A17  
29 WE#  
28 A13  
27 A8  
A18  
A17  
A16  
A15  
OE#  
I/O7  
I/O6  
GND  
A6  
A5  
7
26 A9  
A4  
A3  
A2  
A1  
8
9
25 A11  
24 CS2#  
23 A10  
22 CS1#  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
V
CC  
9
GND  
I/O2  
I/O3  
WE#  
A5  
A6  
A7  
A8  
A9  
10  
11  
12  
13  
14  
15  
16  
17  
18  
VCC  
10  
11  
12  
13  
14  
15  
16  
I/O5  
I/O4  
A14  
A13  
A12  
A11  
A0  
I/O0  
I/O1  
I/O2  
GND  
A10  
CS2#  
Pin Description  
Pin Description  
A0-18  
I/O0-7  
CS1-2#  
OE#  
Address Inputs  
A0-18  
I/O0-7  
Address Inputs  
Data Input/Output  
Chip Selects  
Output Enable  
Write Enable  
+5.0V Power  
Ground  
Data Input/Output  
CS1-2#  
WE#  
VCC  
Chip Selects  
Write Enable  
+5.0V Power  
Ground  
WE#  
VCC  
GND  
GND  
Block Diagram  
Block Diagram  
I/O0-7  
I/O0-7  
WE#  
OE#  
A0-18  
WE#  
A0-18  
512K x 8  
512K x 8  
512K x 8  
512K x 8  
CS1# (1)  
CS2# (1)  
CS1# (1)  
CS2# (1)  
NOTE:  
1. CS1# and CS2# are used to select the lower and upper 512Kx8 of the device. CS1# and CS2# must not be enabled at the same time.  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
July 2004  
Rev. 5  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  

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