Datasheet > WM8805GEDS

WM8805GEDS

更新时间： 2024-11-23 03:54:39

品牌	Logo	应用领域
欧胜 - WOLFSON		/
页数	文件大小	规格书
65页	848K
描述
8:1 Digital Interface Transceiver with PLL

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WM8805GEDS 技术参数

生命周期：	Transferred	Reach Compliance Code：	unknown
风险等级：	5.61	Base Number Matches：	1

WM8805GEDS 数据手册

WM8805

8:1 Digital Interface Transceiver with PLL

DESCRIPTION

FEATURES

•

S/PDIF (IEC60958-3) compliant.

The WM8805 is a high performance consumer mode

S/PDIF transceiver with support for 8 received Channels

and 1 transmitted Channel.

Advanced jitter attenuating PLL with low intrinsic period

jitter of 50 ps RMS.

•

S/PDIF recovered clock using PLL, or stand alone crystal

derived clock generation.

A crystal derived, or externally provided high quality master

clock is used to allow low jitter recovery of S/PDIF supplied

master clocks.

•

Supports 10 – 27MHz crystal clock frequencies.

2-wire / 3-Wire serial or hardware control interface.

Programmable Audio data interface modes:

Generation of all typically used audio clocks is possible

using the high performance internal PLL. A dedicated

CLKOUT pin provides a high drive clock output.

I²S, Left, Right Justified or DSP

16/20/24 bit word lengths

A pass through option is provided which allows the device

simply to be used to clean up (de-jitter) the received digital

audio signals.

•

8 channel receiver input and 1 channel transmit output.

Auto frequency detection / synchronisation.

Selectable output status data bits.

The device may be used under software control or stand

alone hardware control modes. In software control mode,

both 2-wire with read back and 3-wire interface modes are

supported.

Up to 8 configurable GPO pins.

De-emphasis flag output.

Non-audio detection including DOLBY^TMand DTS^TM

Channel status changed flag.

Status and error monitoring is built-in and results can be

read back over the control interface, on the GPO pins or

streamed over the audio data interface in ‘With Flags’ mode

(audio data with status flags appended).

Configurable clock distribution with selectable output

MCLK rate of 512fs, 256fs, 128fs and 64fs.

•

2.7 to 3.6V digital and PLL supply voltages.

28-lead SSOP package.

The audio data interface supports I²S, left justified, right

justified and DSP audio formats of 16-24 bit word length,

with sample rates from 32 to 192ks/s.

APPLICATIONS

•

Surround Sound AV processors and Hi-Fi systems

Music industry applications

DVD-P/DVD-RW

The device is supplied in a 28-lead Pb-free SSOP package.

Digital TV

BLOCK DIAGRAM

WOLFSON MICROELECTRONICS plc

Production Data, September 07, Rev 4.1

To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/

12 3 4 5 6 7...65

中文翻译

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