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WF2M16W-120I5A

更新时间： 2022-04-23 23:00:11
品牌 Logo 应用领域
WEDC 闪存
页数 文件大小 规格书
12页 276K
描述
2Mx16 Flash MODULE, SMD 5962-97610

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WF2M16W-120I5A 数据手册

 浏览型号WF2M16W-120I5A的Datasheet PDF文件第2页浏览型号WF2M16W-120I5A的Datasheet PDF文件第3页浏览型号WF2M16W-120I5A的Datasheet PDF文件第4页浏览型号WF2M16W-120I5A的Datasheet PDF文件第5页浏览型号WF2M16W-120I5A的Datasheet PDF文件第6页浏览型号WF2M16W-120I5A的Datasheet PDF文件第7页 
WF2M16-XXX5  
White Electronic Designs  
PRELIMINARY*  
2Mx16 Flash MODULE, SMD 5962-97610  
FEATURES  
ꢀ
ꢀ
Access Times of 90, 120, 150ns  
Packaging:  
ꢀ
ꢀ
Low Power CMOS  
Data# Polling and Toggle Bit feature for detection of  
program or erase cycle completion.  
Supports reading or programming data to a sector  
not being erased.  
Built-in Decoupling Caps and Multiple Ground Pins  
for Low Noise Operation.  
RESET# pin resets internal state machine to the  
read mode.  
Ready/Busy (RY#/BY#) output for detection of  
program or erase cycle completion.  
•
56 lead, Hermetic Ceramic, 0.520" CSOP  
(Package 207).  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Fits standard 56 SSOP footprint.  
•
•
44 pin Ceramic SOJ (Package 102)**  
44 lead Ceramic Flatpack (Package 208)**  
ꢀ
Sector Architecture  
•
•
32 equal size sectors of 64KBytes each  
Any combination of sectors can be erased.  
Also supports full chip erase.  
Multiple Ground Pins for Low Noise Operation  
ꢀ
ꢀ
ꢀ
Minimum 100,000 Write/Erase Cycles Minimum  
Organized as 2Mx16; User Configurable as 2 x 2Mx8  
* This product is under development, is not qualified or characterized and is subject to  
change without notice.  
** Package to be developed.  
Commercial, Industrial, and Military Temperature  
Ranges  
ꢀ
5 Volt Read and Write. 5V 10ꢀ Supply.  
Note: For programming information refer to Flash Programming 16M5 Application Notes.  
FIGURE 1 – PIN CONFIGURATIONS  
WF2M16-XDAX5  
56 CSOP  
WF2M16-XXX5  
44 CSOJ (DL)**  
PIN DESCRIPTION  
I/O0-15  
A0-20  
WE#  
Data Inputs/Outputs  
Address Inputs  
Write Enable  
Chip Select  
Output Enable  
Power Supply  
Ground  
44 FLATPACK (FL)**  
TOP VIEW  
TOP VIEW  
CS1#  
A12  
A13  
A14  
A15  
NC  
CS2#  
NC  
A20  
A19  
A18  
A17  
A16  
VCC  
GND  
I/O6  
I/O14  
I/O7  
I/O15  
RY/BY#  
OE#  
WE#  
NC  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
CS1#  
A12  
A13  
A14  
A15  
NC  
CS2#  
NC  
A20  
A19  
A18  
A17  
A16  
VCC  
GND  
I/O6  
I/O14  
I/O7  
I/O15  
RY/BY#  
OE#  
WE#  
NC  
I/O13  
I/O5  
I/O12  
I/O4  
VCC  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
NC  
NC  
CS1-2  
#
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
#RESET  
A11  
A10  
A9  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
GND  
A8  
VCC  
I/O9  
I/O1  
#RESET  
A11  
A10  
A9  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
GND  
A8  
VCC  
I/O9  
I/O1  
OE#  
VCC  
VSS  
RY/BY#  
RESET#  
Ready/Busy  
Reset  
BLOCK DIAGRAM  
I/O0-7  
I/O8-1  
RESET#  
39 I/O8  
38 I/O0  
37 A0  
36 NC  
35 NC  
34 NC  
33 I/O2  
WE#  
OE#  
0-20  
A
RY/BY#  
I/O13  
I/O5  
I/O12  
I/O4  
VCC  
I/O10  
I/O3  
I/O11  
GND  
32  
31  
30  
29  
2M x 8  
2M x 8  
CS1#  
CS2#  
** Package to be developed.  
NOTE:  
1. RY/BY# is an open drain output and should be pulled up to Vcc with an external resistor.  
2. Address compatible with Intel 2M8 56 SSOP.  
April 2004  
Rev. 5  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
1234567...12

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