WED3DG644V-D1
White Electronic Designs
AC OPERATING TEST CONDITIONS
VCC = 3.3V ± 0.3V, 0 ≤ TA ≤ 70°C
Parameter
Value
Unit
V
AC input levels (VIH/VIL)
2.4/0.4
1.4
Input timing measurement reference level
Input rise and fall time
V
tR/tF = 1/1
1.4
ns
V
Output timing measurement reference level
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
7.5, 10
Row active to row active delay
RAS# to CAS# delay
tRRD (min)
tRCD (min)
15
ns
ns
1
1
1
1
20
Row precharge time
t
RP (min)
20
ns
tRAS (min)
45
ns
Row active time
t
RAS (max)
tRC (min)
tRDL (min)
100
us
Row cycle time
65
ns
1
2
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
2
CLK
—
t
DAL (min)
2 CLK + tRP
tCDL (min)
tBDL (min)
tCCD (min)
1
1
1
2
1
CLK
CLK
CLK
2
2
3
Col. address to col. address delay
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
Notes :
1.
2.
3.
4.
The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.
Minimum delay is required to complete write.
All parts allow every cycle column address change.
In case of row precharge interrupt, auto precharge and read burst stop.
June 2006
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com