W.A.R.P. 1.1
WEIGHT ASSOCIATIVE RULE PROCESSOR
ADVANCED DATA
High Speed Rules Processing
Antecedent Membership Functions with any
Shape
Up to 256 Rules (4 Antecedents,1
Consequent)
Up to 16 Input ConfigurableVariables
Up to 16 Membership Functions for an Input
Variable
Up to 16 OutputVariables
Up to 128 Membership Functions for all
Consequents
CPGA 100
PLCC84
MAX-DOT Inference Method
Defuzzification on chip
Figure 1. Logic Diagram
MCLK VS S VDD
Software Tools and Emulators Availability
100-pin CPGA100 Ceramic Package
84-lead Plastic Leaded Chip Carrier package
GENERAL DESCRIPTION
10
FIN
W.A.R.P. is a VLSI Fuzzy Logic controller whose
architecture arises from the need of realizing an
integrated structure with high inferencing perform-
ances andflexibility. To get those results a modular
architecture based on a set of parallel memory
blocks has been implemented.
In orderto obtainhigh performancesW.A.R.P.uses
different data representations during the various
phases of the computational cycle, so that it is
always operating on the optimal data repre-
sentation. A vectorial characterization has been
adopted for the Antecedent Membership Func-
tions. W.A.R.P. exploits a SGS-THOMSON pat-
entedstrategyto store the AntecedentMembership
O0-O9
SYNC
4
8
OCNT0-OCNT3
I0-I7
EPA0-EPA2
A0-A9
W.A.R.P.
1.1
3
STB
NP
10
EP
CHM OFL PRST
Table 1. W.A.R.P. Configuration Settings
Number of Inputs
Configurable [1..8]
Standard Rule Format
Rules Number
4 Antecedents, 1 Consequent [or subsets]
Max 256 Rules in the 4 Antecedent, 1 Consequent format
Antecedent’s MFs Number
Consequent’s MFs Number
Input Data Resolution
Output Data Resolution
Configurable [up to 16 for an input variable]
Max 256 for all outputs variables
8 bit
8 bit
1/19
May 1996
This is advance information on a new productnow in development or undergoing evaluation. Details are subject to change without notice.