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W83194BR-903

1. GENERAL DESCRIPTION

The W83194BR-903 is a Clock Synthesizer for VIA PT880/PM880 chipset. W83194BR-903 provides

all clocks required for high-speed microprocessor and provides step-less frequency programming and

32 different frequencies of CPU, PCI, and AGP clocks setting, support two 25MHz clock outputs, all

clocks are externally selectable with smooth transitions.

The W83194BR-903 provides I²C serial bus interface to program the registers to enable or disable

each clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable

S.S.T. scale to reduce EMI.

The W83194BR-903 also has watchdog timer and reset output pin to support auto-reset when

systems hanging caused by improper frequency setting.

The W83194BR-903 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.

2. PRODUCT FEATURES

•

3 0.7V current-mode Differential pairs clock outputs

2 2.5V 25MHz clock outputs

3 AGP clock outputs

10 PCI synchronous clocks

1 24_48MHz clock output for super I/O.

1 48 MHz clock output for USB.

2 14.318MHz REF clock outputs.

AGP/PCI clock out supports synchronous and asynchronous mode

Smooth frequency switch with selections from 100 to 400MHz

Step-less frequency programming

I²C 2-Wire serial interface and support byte read/write and block read/write.

-0.5% and +/- 0.25% center type spread spectrum

Programmable S.S.T. scale to reduce EMI

Programmable registers to enable/stop each output and select modes

Programmable clock outputs Slew rate control and Skew control

Watch Dog Timer and RESET# output pins

48-pin SSOP package

Publication Release Date: April 13, 2005

Revision 1.1

- 1 -

W83194BR-903

3. PIN CONFIGURATION

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

VDDA

GND

IREF

CPUT_ITP

CPUC_ITP

GND

CPUT1

CPUC1

FS1* /REF0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

FS0^&/REF1

VDDREF

XIN

XOUT

GND

FS2^&/PCI_F0

FS4^&/PCI_F1

PCI_F2

VDDPCI

GND

MODE ^&/PCI0

PCI1

VDDCPU

CPUT0

CPUC0

GND

25MHz_0

25MHz_1

VDD2.5

VTT_PWRGD/PD#*

SDATA*

SCLK*

RESET#

AGP_0

GND

PCI2

PCI3

PCI4

VDDPCI

GND

PCI_STOP#*/PCI5

CPU_STOP#*/PCI6

FS3^&/48MHz

SEL24_48# ^&/24_48MHz

GND

VDDAGP

AGP_1

AGP_2

VDD48

#: Active low

*: Internal pull up resistor 120K to VDD

&: Internal Pull-down resistor 120K to GND

4. BLOCK DIAGRAM

48MHz

PLL2

Divider

24_48MHz

2

XTAL

OSC

XIN

XOUT

REF 0:1

PLL1

Spread

Spectrum

2

VCOCLK

CPUT0:1

CPUC0:1

CPUT_ITP

CPUC_ITP

M/N/Ratio

ROM

2

25MHz_0:1

AGP0:2

Divider

3

VTT_PWRGD

FS(0:4)

MODE

Latch

&POR

&

10

SEL24_48#

PCI_F0:2,PC

I_0:6

PD#*

Control

Logic

PCI_STOP#*

CPU_STOP#*

RESET#

Rref

&Config

Register

SDATA*

SCLK*

I2C

Interface

- 2 -

W83194BR-903

5. PIN DESCRIPTION

BUFFER TYPE SYMBOL

DESCRIPTION

IN

IN_tp120k

IN_td120k

OUT

OD

Input

Latched input at power up, internal 120kΩ pull up.

Latched input at power up, internal 120kΩ pull down.

Output

Open Drain

I/OD

#

Bi-directional Pin, Open Drain.

Active Low

*

Internal 120kΩ pull-up

&

Internal 120 kΩ pull-down

5.1 Crystal I/O

PIN NAME

TYPE

DESCRIPTION

Crystal input with internal loading capacitors (18pF) and feedback

resistors.

4

XIN

IN

Crystal output at 14.318MHz nominally with internal loading

capacitors (18pF).

5

XOUT

OUT

5.2 CPU, AGP, and PCI Clock Outputs

PIN NAME

CPUT [0:1]

CPUC [0:1]

TYPE

DESCRIPTION

42, 39, 41,

38

Low skew (< 250ps) differential clock outputs for host

frequencies of CPU

OUT

CPUT_ITP,

CPUC_ITP

45, 44

OUT

Differential clock outputs for host frequencies of CPU

29, 26, 25

AGP0: 2

PCI_F0

OUT

3.3V AGP clock outputs.

3.3V PCI free running clock output.

7

8

Latched input for FS2 at initial power up for H/W selecting the

output frequency. This is internal 120K pull down.

3.3V PCI free running clock output.

Latched input for FS4 at initial power up for H/W selecting the

output frequency, This is internal 120K pull down.

3.3V PCI clock output.

FS2&

PCI_F1

FS4&

INtd120k

OUT

INtd120k

OUT

PCI0

Latched input for pin 19, 20 at initial power up selecting the

0=PCI5, PCI6 clock output, 1=PCI_STOP and CPU _STOP

control pin. This is internal 120KΩ pull down.

12

MODE&

INtd120k

Publication Release Date: April 13, 2005

- 3 -

Revision 1.1

W83194BR-903

CPU, AGP, and PCI Clock Outputs, continued

PIN NAME

TYPE

DESCRIPTION

9

PCI_F2

OUT

3.3V PCI free running clock output.

3.3V PCI clock output. Select by pin 12 MODE^&power up

initial =0.

PCI5

OUT

19

Active low, Stop all PCI clock output besides the free running

PCI_STOP#* IN_tp120k

PCI6 OUT

clocks. Select by pin 12 MODE^&power up initial =1.

3.3V PCI clock output. Select by pin 12 MODE^&power up

initial =0.

20

Active low, Stop all CPU clock outputs. Select by pin 12

CPU_STOP#* IN_tp120k

13,14,15,16 PCI [1:4] OUT

MODE^&power up initial =1.

Low skew (< 250ps) PCI clock outputs.

5.3 Fixed Frequency Outputs

PIN NAME

TYPE

DESCRIPTION

REF0

OUT

14.318MHz output.

1

Latched input for FS1 at initial power up for H/W selecting the

FS1*

REF1

FS0^&

IN_tp120k

OUT

output frequency. This is internal 120K pull up.

14.318MHz output.

2

Latched input for FS0 at initial power up for H/W selecting the

IN_td120k

OUT

output frequency. This is internal 120K pull down.

48MHz

FS3^&

48MHz clock output for USB.

21

Latched input for FS3 at initial power up for H/W selecting the

IN_td120k

output frequency. This is internal 120K pull down.

24MHz or 48MHz(default) clock output, In power on reset

period, it is a hardware-latched pin, and it can be R/W by I2C

control after power on reset period. Select by register 5 bit 7.

Latched input for 24MHz or 48MHz select pin. This is internal

120K pull down default 48MHz. In power on reset period, it is a

hardware-latched pin, and it can be R/W by I2C control after

power on reset period. Select by register 5 bit 7.

24_48MHz

OUT

22

SEL24_48#^&

IN_td120k

OUT

36, 35 25MHz_[0:1]

25MHz 2.5V push pull clock output.

5.4 I2C Control Interface

PIN NAME

TYPE

DESCRIPTION

Serial data of I²C 2-wire control interface with internal 120K pull-

up resistor.

32

SDATA*

I/OD

Serial clock of I²C 2-wire control interface with internal 120K

pull-up resistor.

31

SCLK*

IN_tp120k

- 4 -

W83194BR-903

5.5 Power Management Pins

PIN NAME

TYPE

DESCRIPTION

Power good input signal is power on trapping with HIGH active.

This 3.3V input is level sensitive strobe used to determine FS

[4:0]. This pin is HIGH active.

Power Down Function. This is power down pin, low active (PD#).

Internal 120K pull up

VTT_PWRGD

IN

33

PD#*

IN_tp120k

Deciding the reference current for the CPUCLK pairs. The pin

was connected to the precision resistor tied to ground to decide

the appropriate current.

System reset signal when the watchdog is time out. This pin will

generate 250ms low phase when the watchdog timer is timeout.

46

30

IREF

OUT

OD

RESET#

5.6 IREF selects Function

OUTPUT

CURRENT

BOARD TARGET

TRACE/TERM Z

REFERENCE R,

VOH @ Z

IREF = ADD/(3*RR)

Rr = 221 1%

IREF = 5.00mA

Rr = 475 1%

Ioh = 4*IREF

Ioh = 6*IREF

1.0V @ 50

0.7V @ 50

50 Ω

IREF = 2.32mA

5.7 Power Pins

PIN NAME

VDDREF

VDDPCI

VDDAGP

VDDCPU

VDD48

TYPE

DESCRIPTION

3

PWR

3.3V power supply for REF.

10,17

27

40

24

34

3.3V power supply for PCI.

3.3V power supply for AGP.

3.3V power supply for CPU.

3.3 power supply for 48MHz.

2.5V power supply for 25MHz.

3.3V power for Analog power

VDD2.5

VDDA

48

6, 11, 18, 23,

28, 37, 43, 47

GND

PWR

Ground pin

Publication Release Date: April 13, 2005

Revision 1.1

- 5 -

W83194BR-903

6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE

This frequency table is used at power on latched FS [4:0] value or software programming at SSEL

[4:0] (Register 0 bit 7 ~ 3).

FS4

0

FS3

0

FS2

0

FS1

0

FS0

0

CPU (MHZ)

100.00

200.01

133.34

200.01

400.01

266.68

101.1

3V66 (MHZ)

66.67

67.34

66.67

70.02

PCI (MHZ)

33.33

33.67

33.33

35.01

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

202.2

0

1

0

1

0

134.68

100.00

200.01

133.34

200.01

400.01

266.68

105.04

210.07

140.05

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

- 6 -

W83194BR-903

7. I²C CONTROL AND STATUS REGISTERS

7.1 Register 0: Frequency Select (Default = 10h)

BIT

7

6

5

4

NAME

PWD

DESCRIPTION

SSEL [4]

SSEL [3]

SSEL [2]

SSEL [1]

SSEL [0]

0

1

0

Frequency selection by software via I²C

3

Enable software program FS [4:0].

0 = Select frequency by hardware.

2

1

0

EN_SSEL

EN_SPSP

0

1= Select frequency by software I²C - Bit 7~ 3.

Enable Spread Spectrum in the frequency table.

0 = Normal

1 = Spread Spectrum Enabled

Enable reload safe frequency when the watchdog is timeout.

0 = reload the FS [4:0] latched pins when watchdog time out.

1 = reload the safe frequency bit defined at Register 5 bit 4~0.

EN_SAFE_FREQ

7.2 Register 1: CPU Clock (1 = Enable, 0 = Stopped) (Default: E2h)

BIT

7

PIN NO

45, 44

PWD

1

DESCRIPTION

CPUT_IPT/CPUC_IPT output control.

6

42, 41

1

CPUT1 / C1 output control.

5

39, 38

1

CPUT0 / C0 output control.

4

3

2

1

-

X

Power on latched value of FS4 pin. Default: 0 (Read only)

Power on latched value of FS3 pin. Default: 0 (Read only)

Power on latched value of FS2 pin. Default: 0 (Read only)

Power on latched value of FS1 pin. Default: 1 (Read only)

Power on latched value of FS0 pin. Default: 0 (Read only)

0

X

Publication Release Date: April 13, 2005

Revision 1.1

- 7 -

W83194BR-903

7.3 Register 2: PCI Clock (1 = Enable, 0 = Stopped) (Default: FFh)

BIT

7

6

5

4

3

2

1

0

PIN NO

PWD

DESCRIPTION

9

8

7

1

PCI_F2 output control.

PCI_F1 output control.

PCI_F0 output control.

Reserved

PCI6 output control.

PCI5 output control.

PCI4 output control.

PCI3 output control.

Reserve

20

19

16

15

7.4 Register 3: PCI, AGP Clock (1 = Enable, 0 = Stopped) (Default: FFh)

BIT

7

6

5

4

3

2

1

0

PIN NO

PWD

DESCRIPTION

14

13

12

-

25

26

29

-

1

PCI2 output control.

PCI1 output control.

PCI0 output control.

Don’t modify it

AGP_2 output control.

AGP_1 output control.

AGP_0 output control.

Don’t modify it

7.5 Register 4: 24_48MHz, 48MHz, REF, 25MHz Control (1 = Enable, 0 = Stopped)

(Default: BFh)

BIT

7

6

5

4

3

2

1

0

PIN NO

PWD

DESCRIPTION

22

-

21

-

2

1

0

1

24_48MHz output control.

Reserved

48MHz output control.

Reserved

REF1 output control.

REF0 output control.

25MHz_1 output control.

25MHz_0 output control.

35

36

- 8 -

W83194BR-903

7.6 Register 5: Watchdog Control (Default: 02h)

BIT

NAME

PWD

DESCRIPTION

24 / 48 MHz output selection, 1: 24 MHz.0: 48 MHz. (Default)

Default value follow hardware trapping data on SEL24_48# pin.

Program this bit =>

7

SEL24_48

X

1: Enable Watchdog Timer feature.

0: Disable Watchdog Timer feature.

Read-back this bit =>

6

EN_WD

0

During timer count down the bit read back to 1.

If count to zero, this bit read back to 0.

Read Back only, Timeout Flag, This bit is Read Only.

1: Watchdog has ever started and counts to zero.

0: Watchdog is restarted and counting.

5

WD_TIMEOUT

0

4

3

2

1

0

SAF_FREQ [4]

SAF_FREQ [3]

SAF_FREQ [2]

SAF_FREQ [1]

SAF_FREQ [0]

0

1

0

These bits will be reloaded in Reg-0 to select frequency table. As the

watchdog is timeout and EN_SAFE_FREQ=1.

7.7 Register 6: Reserved (Default: 50h) (Read Only)

BIT

7

6

5

4

3

2

1

0

NAME

PWD

DESCRIPTION

Reserved

0

1

0

1

0

Reserved

Publication Release Date: April 13, 2005

Revision 1.1

- 9 -

W83194BR-903

7.8 Register 7: Winbond Chip ID (Default: 70h) (Read Only)

BIT

7

6

5

4

3

2

1

0

NAME

PWD

DESCRIPTION

Winbond Chip ID. W83194BR-903 (SA5870)

Winbond Chip ID.

CHPI_ID [7]

CHPI_ID [6]

CHPI_ID [5]

CHPI_ID [4]

CHPI_ID [3]

CHPI_ID [2]

CHPI_ID [1]

CHPI_ID [0]

0

1

0

Winbond Chip ID.

7.9 Register 8: M/N Program (Default: 90h)

BIT

7

6

5

4

3

2

1

0

NAME

PWD

DESCRIPTION

N_DIV [8]

M_DIV [6]

M_DIV [5]

M_DIV [4]

M_DIV [3]

M_DIV [2]

M_DIV [1]

M_DIV [0]

1

0

1

0

Programmable N divisor value. Bit 7 ~0 are defined in the Register 9.

Programmable M divisor value.

7.10 Register 9: M/N Program (Default: 7Ah)

BIT

7

6

5

4

3

2

1

0

NAME

PWD

DESCRIPTION

N_DIV [7]

N_DIV [6]

N_DIV [5]

N_DIV [4]

N_DIV [3]

N_DIV [2]

N_DIV [1]

N_DIV [0]

0

1

0

1

0

Programmable N divisor value bit 7 ~0. The bit 8 is defined in

Register 8.

- 10 -

W83194BR-903

7.11 Register 10: M/N Program (Default: BBh)

BIT

7

6

5

4

3

2

1

0

NAME

N_DIV [9]

N3<6>

N3<5>

N3<4>

N3<3>

N3<2>

N3<1>

N3<0>

PWD

DESCRIPTION

Programmable N divisor bit 9.

1

0

1

0

1

Programmable N3 divisor bit 6 ~0 for programmable 25M clocks.

M3 = 10000 (Fix)

Frequency range: 21.7M ~ 28.8M

Resolution: 56K

7.12 Register 11: Spread Spectrum Programming (Default: 0Bh)

BIT

7

6

5

4

3

2

1

0

NAME

SP_UP [3]

SP_UP [2]

SP_UP [1]

PWD

DESCRIPTION

0

1

0

1

Spread Spectrum Up Counter bit 3 ~ bit 0.

SP_UP [0]

SP_DOWN [3]

SP_DOWN [2]

SP_DOWN [1]

SP_DOWN [0]

Spread Spectrum Down Counter bit 3 ~ bit 0

2’s complement representation.

Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000

7.13 Register 12: Divisor and Step-less Enable Control (Default: FBh)

BIT

7

6

5

4

3

2

1

0

NAME

Reserved

DS9

PWD

DESCRIPTION

1

0

1

Reserved

Define the AGP divider ratio

Table-2 integrate the all divider configuration

DS5

Reserved

DS2

Reserved

Define the CPU divider ratio

Refer to Table-2

DS1

DS0

Publication Release Date: April 13, 2005

Revision 1.1

- 11 -

W83194BR-903

Table-2 CPU, AGP, PCI divider ratio selection Table

AGP

Bit5

CPU

Bit1, 0

LSB

MSB

0

1

00

01

10

Div4

Div8

11

Div6

Div8

Bit2/

Bit9

0

1

Div6

Div10

Div7

Div12

Div2

Div8

Div3

Div8

7.14 Register 13: Divisor and Step-less Enable Control (Default: 0Fh)

BIT

NAME

PWD

DESCRIPTION

0: Output frequency depend on frequency table

1: Program all clock frequency by changing M/N value

The equation is

VCO =14.318MHz*(N+4)/ M.

7

EN_MN_PROG

0

Once the watchdog timer timeout, the bit will be clear. Then the

frequency will be decided by hardware default FS<4:0> or desired

frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ (Reg0

- bit 0).

6

5

4

3

2

1

0

Reserved

IVAL<3>

IVAL<2>

IVAL<1>

IVAL<0>

0

1

Reserved

Charge pump current selection

7.15 Register 14: Control (Default: 0Ah)

BIT

NAME

PWD

DESCRIPTION

CPUT output state in during POWER DOWN or Stop mode assertion.

1: Driven (2*Iref),

7

CPUT_DRI

0

0: Tristate (Floating)

CPUC always tri-state (floating) in power down Assertion.

6

5

4

3

2

1

0

Reserved

SPCNT [5]

SPCNT [4]

SPCNT [3]

SPCNT [2]

SPCNT [1]

SPCNT [0]

0

1

0

1

0

Reserved

Spread Spectrum Programmable time, the resolution is 280ns. Default

period is 11.8us

- 12 -

W83194BR-903

7.16 Register 15: SST & Skew Control (Default: 2Ch)

BIT

7

6

NAME

INV_CPU

Reserved

PWD

0

DESCRIPTION

Invert the CPU phase, 0: Default, 1: Inverse

Reserved

Spread spectrum implementation method

1: Pendulum type, 0: Original

Spread Spectrum type select.

5

4

SPSP_TYPE

SPSP1

1

0

00: Down

1%

01: Down 0.5%

10: Center +/- 0.5%

11: Center +/- 0.25%

3

SPSP0

1

2

1

0

ASKEW [2]

ASKEW [1]

ASKEW [0]

1

0

CPU to AGP skew control, Skew resolution is 340ps

Expand the skew direction is same as

CPU_AGP_SKEW [2:0] setting

7.17 Register 16: Skew Control (Default: 24h)

BIT

7

6

5

4

3

2

1

0

NAME

INV_AGP

INV_PCI

Reserved

PSKEW [2]

PSKEW [1]

PSKEW [0]

PWD

DESCRIPTION

Invert the AGP phase, 0: Default, 1: Inverse

Invert the PCI phase, 0: Default, 1: Inverse

0

1

0

1

0

Reserved

CPU to PCI skew control, Skew resolution is 340ps

Expand the skew direction is same as

CPU_PCI_SKEW [2:0] setting

7.18 Register 17: Slew rate Control (Default: 00h)

BIT

7

6

5

4

3

2

1

0

NAME

PWD

DESCRIPTION

PCI_F2_S2

PCI_F2_S1

PCI_F0_S2

PCI_F0_S1

AGP_2_S2

AGP_2_S1

AGP_10_S2

AGP_10_S1

0

PCI_F2 slew rate control

11: Strong, 00: Weak, 10/01: Normal

PCI_F1 / PCI_F0 slew rate control

11: Strong, 00: Weak, 10/01: Normal

AGP2 slew rate control

11: Strong, 00: Weak, 10/01: Normal

AGP_1 /AGP_0 slew rate control

11: Strong, 00: Weak, 10/01: Normal

Publication Release Date: April 13, 2005

Revision 1.1

- 13 -

W83194BR-903

7.19 Register 18: Slew rate Control (Default: 00h)

BIT

7

6

5

4

3

2

1

0

NAME

PWD

DESCRIPTION

PCI_65_S2

PCI_65_S1

PCI_42_S2

PCI_42_S1

PCI_10_S2

PCI_10_S1

REF_S2

0

PCI6, 5 slew rate control

11: Strong, 00: Weak, 10/01: Normal

PCI4, 3,2 slew rate control

11: Strong, 00: Weak, 10/01: Normal

PCI1, 0 slew rate control

11: Strong, 00: Weak, 10/01: Normal

REF0, 1 slew rate control

11: Strong, 00: Weak, 10/01: Normal

REF_S1

7.20 Register 19: Slew rate Control (Default: D2h)

BIT

7

6

5

4

NAME

PWD

DESCRIPTION

CPU1STOP_EN

CPU0STOP_EN

25MHz_S2

1

0

1

Stop CPU1 clocks, 1: Enable stop feature, 0: Disable

Stop CPU0 clocks, 1: Enable stop feature, 0: Disable

25MHz_1, 0 slew rate control

11: Strong, 00: Weak, 10/01: Normal

Invert the 48MHz phase, 0: In phase with 24_48MHz

1: 180 degrees out of phase

25MHz_S1

3

INV_48MHz

0

2

1

48MHz_S2

48MHz_S1

0

1

48MHz/24_48MHz slew rate control

11: Strong, 00: Weak, 10/01: Normal

Pin 19,20 Mode selection

1: PCI_STOP, CPU_STOP Control pin

0: PCI5, PCI6 (Default)

0

MODE

X

Default value follow hardware trapping data on MODE^&/PCI0 pin.

7.21 Register 20: Watch dog timer (Default: 08h)

BIT

NAME

PWD

DESCRIPTION

SRC frequency select, 00/01: 25MHz(Default), 10: 100mhZ, 11:

200MHz

7

SRCF1

0

6

5

4

WD_TIME [6]

WD_TIME [5]

WD_TIME [4]

0

Setting the down count depth. One bit resolution represents 250ms.

Default time depth is 8*250ms = 2.0 second. If the watchdog timer is

counting, this register will return present down count value

- 14 -

W83194BR-903

Register 20: Watch dog timer (Default: 08h), continued

BIT

3

2

1

0

NAME

PWD

DESCRIPTION

WD_TIME [3]

WD_TIME [2]

WD_TIME [1]

WD_TIME [0]

1

0

7.22 Register21: Fix Mode Control (Default: 00h)

BIT

7

6

NAME

PWD

DESCRIPTION

Tri-state

Reserved

0

Tri-state all output if set 1

Don’t modify it

5

AGP output frequency select mode

4

FIX_SEL

0

0: Output frequency according to frequency selection table

1: Output frequency according to FIX frequency Reg21 bit 0~2

SRC frequency select

3

2

1

SRCF0

ASEL_2

ASEL_1

0

Asynchronous AGP/PCI frequency table selection ASEL_<2:0>

001: 66 / 33M

011: 88 / 44M

101: 66 / 33M

111: 88 / 33M

010: 75.43 / 37.7M

100: 88 / 44M

110: 75.43 / 33M

000: Clock from PLL1

0

ASEL_0

0

Publication Release Date: April 13, 2005

Revision 1.1

- 15 -

W83194BR-903

8. ACCESS INTERFACE

The W83194BR-903 provides I²C Serial Bus for microprocessor to read/write internal registers. In the

W83194BR-903 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I²C

address is defined at 0xD2.

Block Read and Block Write Protocol

8.1 Block Write Protocol

8.2 Block Read Protocol

## In block mode, the command code must filled 8’h00

8.3 Byte Write Protocol

8.4 Byte Read protocol

- 16 -

W83194BR-903

9. SPECIFICATIONS

9.1 Absolute Maximum Ratings

Stresses greater than those listed in this table may cause permanent damage to the device.

Precautions should be taken to avoid application of any voltage higher than the maximum rated

voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.

Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).

PARAMETER

Absolute 3.3V Core Supply Voltage

Absolute 3.3V I/O Supple Voltage

Operating 3.3V Core Supply Voltage

Operating 3.3V I/O Supple Voltage

Storage Temperature

Ambient Temperature

Operating Temperature

Input ESD protection (Human body model)

RATING

-0.5V to +4.6V

-0.5 V to +4.6 V

3.135V to 3.465V

-65°C to +150°C

-55°C to +125°C

0°C to +70°C

2000V

9.2 General Operating Characteristics

VDDA=VDDAGP=VDDCPU=VDDREF=VDDPCI= 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF

PARAMETER

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

SYM.

V_IL

V_IH

V_OL

V_OH

MIN. MAX.

UNITS

V_dc

TEST CONDITIONS

0.8

2.0

0.4

2.4

All outputs using 3.3V power

CPU = 100 to 400 MHz

Operating Supply Current

I_dd

350

mA

PCI = 33.3 MHz with load

Input pin capacitance

Output pin capacitance

Input pin inductance

Cin

Cout

Lin

5

6

7

pF

nH

9.3 Skew Group Timing Clock

VDDA=VDDAGP=VDDCPU=VDDREF=VDDPCI = 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF

PARAMETER

AGP to PCI Skew

CPU to CPU Skew

AGP to AGP Skew

PCI to PCI Skew

MIN.

1.5

TYP.

2.6

MAX.

3.5

UNITS

ns

ps

TEST CONDITIONS

Measured at 1.5V

Crossing point

Measured at 1.5V

200

250

500

1000

500

48MHz to 48MHz Skew

REF to REF Skew

ps

Publication Release Date: April 13, 2005

Revision 1.1

- 17 -

W83194BR-903

9.4 CPU 0.7V Electrical Characteristics

VDDA=VDDCPU= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=10pF, Vr=475, IREF=2.32mA, Ioh=6*IREF

PARAMETER

Rise Time

Fall Time

Absolute crossing point Voltages

Cycle to Cycle jitter

Duty Cycle

MIN.

175

250

MAX.

700

550

150

55

UNITS

ps

mV

ps

%

TEST CONDITIONS

100 to 200 MHz

100 to 200MHz

45

9.5 AGP Electrical Characteristics

VDDAGP= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

PARAMETER

Rise Time

Fall Time

Cycle to Cycle jitter

Duty Cycle

MIN.

500

MAX.

2000

250

UNITS

ps

%

TEST CONDITIONS

Measure from 0.4V to 2.4V

Measure from 2.4V to 0.4V

Measure 1.5V point

45

55

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-33

mA

Vout=1.0V

Vout=3.135V

Vout=1.95V

Vout=0.4V

-33

38

30

9.6 PCI Electrical Characteristics

VDDPCI= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

PARAMETER

Rise Time

Fall Time

Cycle to Cycle jitter

Duty Cycle

MIN.

500

MAX.

2000

250

UNITS

ps

%

TEST CONDITIONS

Measure from 0.4V to 2.4V

Measure from 2.4V to 0.4V

Measure 1.5V point

45

55

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-33

mA

Vout=1.0V

Vout=3.135V

Vout=1.95V

Vout=0.4V

-33

38

30

- 18 -

W83194BR-903

9.7 24M, 48M Electrical Characteristics

VDD48= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

PARAMETER

Rise Time

Fall Time

MIN.

500

MAX.

2000

500

UNITS

ps

TEST CONDITIONS

Measure from 0.4V to 2.4V

Measure from 2.4V to 0.4V

Measure 1.5V point

Long term jitter

ps

Duty Cycle

45

55

%

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-33

mA

Vout=1.0V

Vout=3.135V

Vout=1.95V

Vout=0.4V

-33

38

30

9.8 REF Electrical Characteristics

VDDREF= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,

PARAMETER

Rise Time

Fall Time

Cycle to Cycle jitter

Duty Cycle

MIN.

1000

MAX.

4000

1000

55

UNITS

ps

%

TEST CONDITIONS

Measure from 0.4V to 2.4V

Measure from 2.4V to 0.4V

Measure 1.5V point

45

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-33

mA

Vout=1.0V

Vout=3.135V

Vout=1.95V

Vout=0.4V

-33

38

30

Publication Release Date: April 13, 2005

Revision 1.1

- 19 -

W83194BR-903

10. ORDERING INFORMATION

PART NUMBER

PACKAGE TYPE

PRODUCTION FLOW

Commercial, 0°C to +70°C

W83194BR-903

48 PIN SSOP

11. HOW TO READ THE TOP MARKING

W83194BR-903

28051234

342GAASA

1st line: Winbond logo and the type number: W83194BR-903

2nd line: Tracking code 2 8051234

2: wafers manufactured in Winbond FAB 2

8051234: wafer production series lot number

3rd line: Tracking code 342 G A A SA

320: packages made in '2003, week 42

G: assembly house ID; O means OSE, G means GR

A: Internal use code

A: IC revision

SA: mask version

All the trademarks of products and companies mentioned in this data sheet belong to their

respective owners.

- 20 -

W83194BR-903

12. PACKAGE DRAWING AND DIMENSIONS

Publication Release Date: April 13, 2005

Revision 1.1

- 21 -

W83194BR-903

13. REVISION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

All of the versions before 0.50 are for internal

use.

n.a.

0.5

0.6

09/07/03

10/28/03

n.a.

6

First published preliminary version.

Modify frequency table

Correction IC version, correction some

description and default value

0.7

12/18/03

7, 9, 19

1.0

1.1

12/23/04

4/13/2005

Update on Web

Add disclaimer

22

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

Headquarters

Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.

27F, 2299 Yan An W. Rd. Shanghai,

200336 China

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

2727 North First Street, San Jose,

CA 95134, U.S.A.

TEL: 1-408-9436666

TEL: 86-21-62365999

FAX: 86-21-62365998

TEL: 886-3-5770066

FAX: 1-408-5441798

FAX: 886-3-5665577

http://www.winbond.com.tw/

Taipei Office

Winbond Electronics Corporation Japan

7F Daini-ueno BLDG, 3-7-18

Shinyokohama Kohoku-ku,

Yokohama, 222-0033

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

TEL: 886-2-8177-7168

FAX: 886-2-8751-3579

TEL: 81-45-4781881

TEL: 852-27513100

FAX: 81-45-4781800

FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

- 22 -

品牌	Logo	应用领域
华邦 - WINBOND		时钟发生器
页数	文件大小	规格书
26页	335K
描述
STEPLESS VIA PT/PM MAIN CLOCK GENERATOR

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SSOP	包装说明：	SSOP, SSOP48,.4
针数：	48	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.81	Is Samacsys：	N
其他特性：	ALSO REQUIRES 2.5V SUPPLY	JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e0	长度：	15.88 mm
端子数量：	48	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	400.01 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装等效代码：	SSOP48,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	240
电源：	3.3 V	主时钟/晶体标称频率：	14.318 MHz
认证状态：	Not Qualified	座面最大高度：	2.79 mm
子类别：	Clock Generators	最大压摆率：	350 mA
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	7.49 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC	Base Number Matches：	1

型号	品牌	描述	获取价格	数据表
W83194BR-903_06	WINBOND	STEPLESS VIA PT/PM MAIN CLOCK GENERATOR	获取价格
W83194BR-911	WINBOND	STEPLESS VIA PT/PM MAIN CLOCK GENERATOR	获取价格
W83194BR-97	WINBOND	200MHZ CLOCK FOR CAMINO CHIPSET	获取价格
W83194BR-B	WINBOND	Stepless Clock Gen. For INTEL Brookdale Chipset	获取价格
W83194BR-C	WINBOND	200MHZ CLOCK FOR CAMINO CHIPSET	获取价格
W83194BR-K8	WINBOND	Processor Specific Clock Generator, 309MHz, CMOS, PDSO48, SSOP-48	获取价格

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