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W3L16C104MAT1A PDF预览

W3L16C104MAT1A

更新时间: 2024-11-29 20:09:07
品牌 Logo 应用领域
京瓷/艾维克斯 - KYOCERA AVX 电容器
页数 文件大小 规格书
4页 158K
描述
Ceramic Capacitor, Multilayer, Ceramic, 6.3V, 20% +Tol, 20% -Tol, X7R, 15% TC, 0.1uF, Surface Mount, 0612, CHIP, ROHS COMPLIANT

W3L16C104MAT1A 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:CHIP, ROHS COMPLIANT
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8532.24.00.20Factory Lead Time:8 weeks
风险等级:5.52电容:0.1 µF
电容器类型:CERAMIC CAPACITOR介电材料:CERAMIC
高度:0.95 mmJESD-609代码:e2
长度:3.2 mm安装特点:SURFACE MOUNT
多层:Yes负容差:20%
端子数量:2最高工作温度:125 °C
最低工作温度:-55 °C封装形状:RECTANGULAR PACKAGE
封装形式:SMT包装方法:TR, 7 INCH
正容差:20%额定(直流)电压(URdc):6.3 V
尺寸代码:0612表面贴装:YES
温度特性代码:X7R温度系数:15% ppm/ °C
端子面层:Tin/Nickel (Sn/Ni)端子形状:WRAPAROUND
宽度:1.6 mmBase Number Matches:1

W3L16C104MAT1A 数据手册

 浏览型号W3L16C104MAT1A的Datasheet PDF文件第2页浏览型号W3L16C104MAT1A的Datasheet PDF文件第3页浏览型号W3L16C104MAT1A的Datasheet PDF文件第4页 
Low Inductance Capacitors  
Introduction  
The signal integrity characteristics of a Power Delivery  
Network (PDN) are becoming critical aspects of board level  
and semiconductor package designs due to higher operating  
frequencies, larger power demands, and the ever shrinking  
lower and upper voltage limits around low operating voltages.  
These power system challenges are coming from mainstream  
designs with operating frequencies of 300MHz or greater,  
modest ICs with power demand of 15 watts or more, and  
operating voltages below 3 volts.  
capacitor, one resistor, and one inductor. The RLC values in  
this model are commonly referred to as equivalent series  
capacitance (ESC), equivalent series resistance (ESR), and  
equivalent series inductance (ESL).  
The ESL of a capacitor determines the speed of energy  
transfer to a load. The lower the ESL of a capacitor, the faster  
that energy can be transferred to a load. Historically, there  
has been a tradeoff between energy storage (capacitance)  
and inductance (speed of energy delivery). Low ESL devices  
typically have low capacitance. Likewise, higher capacitance  
devices typically have higher ESLs. This tradeoff between  
ESL (speed of energy delivery) and capacitance (energy  
storage) drives the PDN design topology that places the  
fastest low ESL capacitors as close to the load as possible.  
Low Inductance MLCCs are found on semiconductor  
packages and on boards as close as possible to the load.  
The classic PDN topology is comprised of a series of  
capacitor stages. Figure 1 is an example of this architecture  
with multiple capacitor stages.  
An ideal capacitor can transfer all its stored energy to a load  
instantly. A real capacitor has parasitics that prevent  
instantaneous transfer of a capacitors stored energy. The  
true nature of a capacitor can be modeled as an RLC  
equivalent circuit. For most simulation purposes, it is possible  
to model the characteristics of a real capacitor with one  
Slowest Capacitors  
Fastest Capacitors  
Semiconductor Product  
VR  
Bulk  
Board-Level  
Package-Level  
Die-Level  
Low Inductance Decoupling Capacitors  
Figure 1 Classic Power Delivery Network (PDN) Architecture  
LOW INDUCTANCE CHIP CAPACITORS  
INTERDIGITATED CAPACITORS  
The key physical characteristic determining equivalent series  
inductance (ESL) of a capacitor is the size of the current loop  
it creates. The smaller the current loop, the lower the ESL. A  
standard surface mount MLCC is rectangular in shape with  
electrical terminations on its shorter sides. A Low Inductance  
Chip Capacitor (LICC) sometimes referred to as Reverse  
Geometry Capacitor (RGC) has its terminations on the longer  
side of its rectangular shape.  
The size of a current loop has the greatest impact on the ESL  
characteristics of a surface mount capacitor. There is a  
secondary method for decreasing the ESL of a capacitor.  
This secondary method uses adjacent opposing current  
loops to reduce ESL. The InterDigitated Capacitor (IDC)  
utilizes both primary and secondary methods of reducing  
inductance. The IDC architecture shrinks the distance  
between terminations to minimize the current loop size, then  
further reduces inductance by creating adjacent opposing  
current loops.  
When the distance between terminations is reduced, the size  
of the current loop is reduced. Since the size of the current  
loop is the primary driver of inductance, an 0306 with a  
smaller current loop has significantly lower ESL then an 0603.  
The reduction in ESL varies by EIA size, however, ESL is  
typically reduced 60% or more with an LICC versus a  
standard MLCC.  
An IDC is one single capacitor with an internal structure that  
has been optimized for low ESL. Similar to standard MLCC  
versus LICCs, the reduction in ESL varies by EIA case size.  
Typically, for the same EIA size, an IDC delivers an ESL that  
is at least 80% lower than an MLCC.  
59  

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