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W211BH PDF预览

W211BH

更新时间: 2024-11-06 21:15:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
15页 298K
描述
Processor Specific Clock Generator, 133.3MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48

W211BH 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP48,.4
针数:48Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.86其他特性:ALSO REQUIRES 2.5V SUPPLY
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:15.875 mm湿度敏感等级:1
端子数量:48最高工作温度:70 °C
最低工作温度:最大输出时钟频率:133.3 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):220
电源:2.5,3.3 V主时钟/晶体标称频率:14.318 MHz
认证状态:Not Qualified座面最大高度:2.794 mm
子类别:Clock Generators最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

W211BH 数据手册

 浏览型号W211BH的Datasheet PDF文件第2页浏览型号W211BH的Datasheet PDF文件第3页浏览型号W211BH的Datasheet PDF文件第4页浏览型号W211BH的Datasheet PDF文件第5页浏览型号W211BH的Datasheet PDF文件第6页浏览型号W211BH的Datasheet PDF文件第7页 
W211B  
FTG for 440BX, VIA Apollo Pro-133, and ProMedia  
Features  
Table 1. Mode Input Table  
• Maximized EMI Suppression using Cypress’s Spread  
Mode  
Pin 2  
CPU_STOP#  
REF0  
Spectrum technology  
0
1
• Single-chip system frequency synthesizer for 440BX,  
VIA Apollo Pro-133, and ProMedia  
• Supports Intel® Pentium® II and Cyrix class processors  
• Two copies of CPU output  
Table 2. Pin Selectable Frequency  
Input Address  
FS3 FS2 FS1 FS0 CPU1 (MHz) (MHz)  
CPU_F,  
PCI_F,1:5 Spread  
• Six copies of PCI output  
• One 48-MHz output for USB  
• One 24-MHz or 48-MHz output for SIO  
• Two buffered reference outputs  
• One IOAPIC output  
Spectrum  
±0.5%  
OFF  
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
133.3  
75  
100.2  
66.8  
79  
110  
115  
120  
133.3  
83  
100.2  
66.8  
122  
129  
138  
95  
33.3  
37.5  
33.3  
33.4  
39.5  
36.7  
38.3  
30  
33.3  
27.7  
33.3  
33.4  
30.5  
32.3  
34.5  
31.7  
±0.5%  
±0.5%  
OFF  
• Thirteen SDRAM outputs provide support for 3 DIMMs  
• Supports frequencies up to 200 MHz  
• SMBus interface for programming  
• Power management control inputs  
• Available in 48-pin SSOP  
OFF  
OFF  
OFF  
–0.5%  
OFF  
• SDRAM Range = 66 MHz to 133 MHz  
Key Specifications  
–0.5%  
–0.5%  
–0.5%  
OFF  
OFF  
–0.5%  
CPU Cycle-to-Cycle Jitter:...........................................250 ps  
CPU to CPU Output Skew:..........................................175 ps  
PCI to PCI Output Skew:.............................................500 ps  
DDQ3:................................................................... 3.3V ± 5%  
DDQ2:................................................................... 2.5V ± 5%  
V
V
SDRAMIN to SDRAM0:12 Delay:........................4.5 – 6.0 ns  
REF0/(CPU_STOP#) Pin Configuration[1]  
VDDQ3  
Block Diagram  
REF1/FS0  
X1  
X2  
XTAL  
OSC  
VDDQ3  
REF0/(CPU_STOP#)  
GND  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDDQ2  
1
IOAPIC  
2
PLL Ref Freq  
REF1/FS0*  
GND  
3
I/O Pin  
X1  
4
Control  
X2  
5
CPU_F  
VDDQ3  
PCI0/MODE  
PCI1/FS1*  
GND  
6
CPU1  
VDDQ2  
7
8
PWRDWN#  
SDRAM12  
GND  
PWRDWN#  
CPU_F  
CPU1  
9
PCI2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
PCI3  
SDRAM0  
SDRAM1  
VDDQ3  
Stop  
Clock  
PCI4  
PLL 1  
Control  
PCI5  
VDDQ3  
SDRAMIN  
GND  
SDRAM2  
SDRAM3  
GND  
÷2,3,4  
VDDQ3  
PCI0/MODE  
PCI1/FS1  
PCI2  
PCI3  
PCI4  
PCI5  
SDRAM11  
SDRAM10  
VDDQ3  
SDRAM9  
SDRAM8  
GND  
SDRAM4  
SDRAM5  
VDDQ3  
SDRAM6  
SDRAM7  
VDDQ3  
SDATA  
48MHz/FS2*  
24_48MHz/FS3^  
SDATA  
SCLK  
SMBus  
Logic  
SMBus  
{
SCLK  
VDDQ3  
48MHz/FS2  
PLL2  
÷2  
24_48MHz/FS3  
VDDQ3  
13  
SDRAMIN  
SDRAM0:12  
Note:  
1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping. Unlike  
other I/O pins, input FS3 has an internal pull-down resistor.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07174 Rev. *B  
Revised October 2, 2003  

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A Major Advance in RTD Technology