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W149

更新时间: 2024-02-04 00:24:22
品牌 Logo 应用领域
SPECTRALINEAR /
页数 文件大小 规格书
15页 202K
描述
440BX AGPset Spread Spectrum Frequency Synthesizer

W149 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:48
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.49
其他特性:ALSO REQUIRES AT 2.5V SUPPLYJESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:15.875 mm
湿度敏感等级:1端子数量:48
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:124 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):220
主时钟/晶体标称频率:14.318 MHz认证状态:Not Qualified
座面最大高度:2.794 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

W149 数据手册

 浏览型号W149的Datasheet PDF文件第3页浏览型号W149的Datasheet PDF文件第4页浏览型号W149的Datasheet PDF文件第5页浏览型号W149的Datasheet PDF文件第7页浏览型号W149的Datasheet PDF文件第8页浏览型号W149的Datasheet PDF文件第9页 
W149  
Writing Data Bytes  
Table 6 details additional frequency selections that are  
available through the serial data interface.  
Each bit in Data Bytes 0–7 control a particular device function  
except for the “reserved” bits which must be written as a logic  
0. Bits are written MSB (most significant bit) first, which is bit 7.  
Table 5 gives the bit formats for registers located in Data Bytes  
0–7.  
Table 7 details the select functions for Byte 0, bits 1 and 0.  
Table 5. Data Bytes 0–7 Serial Configuration Map  
Affected Pin  
Bit Control  
Bit(s)  
Pin No.  
Pin Name  
Control Function  
0
1
Default  
Data Byte 0  
7
6
--  
--  
--  
--  
--  
--  
--  
--  
Don’t Care  
SEL_2  
--  
--  
0
0
--  
--  
--  
--  
--  
--  
See Table 6  
See Table 6  
See Table 6  
5
SEL_1  
0
4
SEL_0  
0
3
Hardware/Software Frequency Select  
Don’t Care  
Hardware  
--  
Software  
--  
0
2
0
1–0  
Bit 1  
Bit 0  
Function (See Table 7 for function details)  
Normal Operation  
(Reserved)  
00  
0
0
1
1
0
1
0
1
Normal Operation  
All Outputs Three-stated  
Data Byte 1  
7
6
5
4
3
2
1
0
--  
--  
(Reserved)  
(Reserved)  
(Reserved)  
(Reserved)  
--  
--  
--  
--  
--  
--  
0
0
0
0
1
0
1
1
--  
--  
--  
--  
--  
--  
--  
--  
40  
--  
SDRAM12  
--  
Clock Output Disable  
(Reserved)  
Low  
--  
Active  
--  
43  
44  
CPU1  
CPU0  
Clock Output Disable  
Clock Output Disable  
Low  
Low  
Active  
Active  
Data Byte 2  
7
6
5
4
3
2
1
0
--  
--  
(Reserved)  
--  
--  
0
1
0
1
1
1
1
1
7
PCI_F  
--  
Clock Output Disable  
(Reserved)  
Low  
--  
Active  
--  
--  
13  
12  
11  
10  
8
PCI5  
PCI4  
PCI3  
PCI2  
PCI1  
Clock Output Disable  
Clock Output Disable  
Clock Output Disable  
Clock Output Disable  
Clock Output Disable  
Low  
Low  
Low  
Low  
Low  
Active  
Active  
Active  
Active  
Active  
Data Byte 3  
7
6
5
4
3
2
--  
--  
--  
(Reserved)  
--  
--  
--  
--  
0
0
1
1
0
1
--  
26  
25  
--  
(Reserved)  
48MHz  
24MHz  
--  
Clock Output Disable  
Clock Output Disable  
(Reserved)  
Low  
Low  
--  
Active  
Active  
--  
21, 20,  
18, 17  
SDRAM8:11 Clock Output Disable  
Low  
Active  
Rev 1.0,November 21, 2006  
Page 6 of 15  

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