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W144

更新时间： 2024-02-08 22:56:32
品牌 Logo 应用领域
SPECTRALINEAR /
页数 文件大小 规格书
13页 201K
描述
440BX AGPset Spread Spectrum Frequency Synthesizer

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中文翻译

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W144 技术参数

是否Rohs认证： 符合生命周期：Active
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8541.40.20.00风险等级：5.77
其他特性：HIGH RELIABILITY颜色：YELLOW
配置：SINGLE最大正向电流：0.03 A
透镜类型：DIFFUSED标称发光强度：3.0 mcd
安装特点：RADIAL MOUNT功能数量：1
端子数量：2最高工作温度：85 °C
最低工作温度：-40 °C光电设备类型：SINGLE COLOR LED
总高度：7 mm包装方法：BULK
峰值波长：590 nm形状：RECTANGULAR
尺寸：3.9 mm表面贴装：NO
端子节距：2.54 mm视角：110 deg
Base Number Matches：1

W144 数据手册

 浏览型号W144的Datasheet PDF文件第7页浏览型号W144的Datasheet PDF文件第8页浏览型号W144的Datasheet PDF文件第9页浏览型号W144的Datasheet PDF文件第10页浏览型号W144的Datasheet PDF文件第11页浏览型号W144的Datasheet PDF文件第13页 
W144  
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)  
CPU = 66.6/100.2 MHz  
Parameter  
Description  
Frequency, Actual  
Output Rise Edge Rate  
Output Fall Edge Rate  
Duty Cycle  
Test Condition/Comments  
Frequency generated by crystal oscillator  
Measured from 0.4V to 2.0V  
Min.  
Typ.  
Max.  
Unit  
MHz  
V/ns  
V/ns  
ꢀ
f
14.31818  
tR  
1
1
–
–
–
–
4
4
tF  
Measured from 2.0V to 0.4V  
tD  
Measured on rising and falling edge at 1.25V  
Assumes full supply voltage reached within  
45  
–
55  
1.5  
fST  
Frequency Stabilization  
ms  
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to  
frequency stabilization.  
Zo  
AC Output Impedance  
Average value during switching transition.  
Used for determining series termination value.  
–
15  
–
:
REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF)  
CPU = 66.6/100.2 MHz  
Parameter  
Description  
Test Condition/Comments  
Min.  
Typ.  
14.318  
–
Max. Unit  
f
Frequency, Actual  
Frequency generated by crystal oscillator  
MHz  
tR  
Output Rise Edge Rate Measured from 0.4V to 2.4V  
0.5  
0.5  
45  
–
2
2
V/ns  
V/ns  
ꢀ
–
tF  
Output Fall Edge Rate  
Duty Cycle  
Measured from 2.4V to 0.4V  
tD  
Measured on rising and falling edge at 1.5V  
–
–
55  
3
fST  
Frequency Stabilization Assumes full supply voltage reached within 1 ms from  
power-up. Short cycles exist prior to frequency stabili-  
zation.  
ms  
from Power-up (cold  
start)  
Zo  
AC Output Impedance  
Average value during switching transition. Used for  
determining series termination value.  
–
40  
–
:
48 MHz Clock Output (Lump Capacitance Test Load = 20 pF = 66.6/100 MHz  
CPU = 66.6/100.2 MHz  
Parameter  
Description  
Test Condition/Comments  
Min.  
Typ.  
Max.  
Unit  
MHz  
ppm  
f
Frequency, Actual  
Determined by PLL divider ratio (see p/q below)  
–48.008–  
fD  
Deviation from 48 MHz (48.008 – 48)/48  
+167  
p/q  
tR  
PLL Ratio  
(14.31818 MHz x 57/17 = 48.008 MHz)  
–57/17  
Output Rise Edge Rate Measured from 0.4V to 2.4V  
Output Fall Edge Rate Measured from 2.4V to 0.4V  
0.5  
0.5  
45  
–
–
–
–
–
2
2
V/ns  
V/ns  
ꢀ
tF  
tD  
Duty Cycle  
Measured on rising and falling edge at 1.5V  
55  
3
fST  
FrequencyStabilization Assumes full supply voltage reached within 1 ms from  
power-up. Short cycles exist prior to frequency stabili-  
zation.  
ms  
from Power-up (cold  
start)  
Zo  
AC Output Impedance Average value during switching transition. Used for  
determining series termination value.  
–
40  
–
:
24 MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz  
CPU = 66.6/100.2 MHz  
Parameter  
Description  
Test Condition/Comments  
Min.  
Typ.  
24.004  
+167  
57/34  
–
Max.  
Unit  
MHz  
ppm  
f
Frequency, Actual  
Determined by PLL divider ratio (see p/q below)  
fD  
Deviation from 24 MHz (24.004 – 24)/24  
p/q  
tR  
PLL Ratio  
(14.31818 MHz x 57/34 = 24.004 MHz)  
Output Rise Edge Rate Measured from 0.4V to 2.4V  
Output Fall Edge Rate Measured from 2.4V to 0.4V  
0.5  
0.5  
45  
2
2
V/ns  
V/ns  
ꢀ
tF  
–
tD  
Duty Cycle  
Measured on rising and falling edge at 1.5V  
–
55  
Rev 1.0,November 21, 2006  
Page 12 of 13  
1...910111213

中文翻译

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