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W144

更新时间： 2024-02-28 23:24:23
品牌 Logo 应用领域
SPECTRALINEAR /
页数 文件大小 规格书
13页 201K
描述
440BX AGPset Spread Spectrum Frequency Synthesizer

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中文翻译

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W144 技术参数

是否Rohs认证： 符合生命周期：Active
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8541.40.20.00风险等级：5.77
其他特性：HIGH RELIABILITY颜色：YELLOW
配置：SINGLE最大正向电流：0.03 A
透镜类型：DIFFUSED标称发光强度：3.0 mcd
安装特点：RADIAL MOUNT功能数量：1
端子数量：2最高工作温度：85 °C
最低工作温度：-40 °C光电设备类型：SINGLE COLOR LED
总高度：7 mm包装方法：BULK
峰值波长：590 nm形状：RECTANGULAR
尺寸：3.9 mm表面贴装：NO
端子节距：2.54 mm视角：110 deg
Base Number Matches：1

W144 数据手册

 浏览型号W144的Datasheet PDF文件第7页浏览型号W144的Datasheet PDF文件第8页浏览型号W144的Datasheet PDF文件第9页浏览型号W144的Datasheet PDF文件第10页浏览型号W144的Datasheet PDF文件第12页浏览型号W144的Datasheet PDF文件第13页 
W144  
SDRAM Clock Outputs, SDRAM, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)  
CPU = 66.6 MHz  
CPU = 100.2 MHz  
Parameter  
tP  
tH  
Description  
Period  
Test Condition/Comments  
Min.  
Typ. Max. Min. Typ. Max. Unit  
Measured on rising edge at 1.5V  
30  
–
–
–
–
30  
–
–
–
–
ns  
ns  
High Time  
Duration of clock cycle above 2.4V, 5.6  
at min. edge rate (1.5V/ns)  
3.3  
tL  
Low Time  
Duration of clock cycle below 0.4V,  
at min. edge rate (1.5V/ns  
5.3  
–
–
–
4
3.1  
1.5  
–
–
–
4
ns  
tR  
Output Rise Edge  
Rate  
Measured from 0.4V to 2.4V  
1.5  
V/ns  
tF  
Output Fall Edge Rate Measured from 2.4V to 0.4V  
1.5  
1
–
–
–
–
4
5
1.5  
1
–
–
–
–
4
5
V/ns  
ns  
tPLH  
tPHL  
tD  
Prop Delay LH  
Prop Delay HL  
Duty Cycle  
Input edge rate faster than 1V/ns  
Input edge rate faster than 1 V/ns  
1
5
1
5
ns  
Measured on rising and falling edge  
at 1.5V,at min. edge rate (1.5 V/ns)  
45  
55  
45  
55  
ꢀ
tJC  
Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V.  
Maximum difference of cycle time  
between two adjacent cycles.  
–
–
250  
–
–
250  
ps  
tSK  
tO  
Output Skew  
Measured on rising edge at 1.5V  
–
–
–
250  
4
–
–
–
250  
4
ps  
ns  
CPU to PCI Clock  
Skew  
Covers all CPU/PCI outputs.  
Measured on rising edge at 1.5V.  
CPU leads PCI output.  
1.5  
1.5  
fST  
Frequency  
Stabilization from  
Power-up (cold start) Short cycles exist prior to frequency  
stabilization.  
Assumes full supply voltage  
reachedwithin1msfrompower-up.  
–
–
–
3
–
–
–
–
3
–
ms  
Zo  
AC Output  
Impedance  
Average value during switching  
transition. Used for determining  
series termination value.  
30  
30  
:
PCI Clock Outputs, PCI_F and PCI1:5 (Lump Capacitance Test Load = 30 pF)  
CPU = 66.6/100.2 MHz  
Parameter  
tP  
Description  
Test Condition/Comments  
Measured on rising edge at 1.5V  
Duration of clock cycle above 2.4V  
Duration of clock cycle below 0.4V  
Measured from 0.4V to 2.4V  
Min.  
29.9  
12.0  
12.0  
1
Typ.  
–
Max.  
Unit  
ns  
Period  
–
–
tH  
tL  
High Time  
–
ns  
Low Time  
–
–
ns  
tR  
tF  
Output Rise Edge Rate  
Output Fall Edge Rate  
Duty Cycle  
–
4
V/ns  
V/ns  
ꢀ
Measured from 2.4V to 0.4V  
1
–
4
tD  
tJC  
Measured on rising and falling edge at 1.5V  
45  
–
55  
250  
Jitter, Cycle-to-Cycle  
Measured on rising edge at 1.5V. Maximum  
difference of cycle time between two  
adjacent cycles.  
–
–
ps  
tSK  
tO  
Output Skew  
Measured on rising edge at 1.5V  
–
–
–
500  
4.0  
ps  
ns  
CPU to PCI Clock Skew  
Covers all CPU/PCI outputs. Measured on  
rising edge at 1.5V. CPU leads PCI output.  
1.5  
fST  
Frequency Stabilization  
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior  
to frequency stabilization.  
Assumes full supply voltage reached within  
–
–
–
3.0  
–
ms  
Zo  
AC Output Impedance  
Average value during switching transition.  
Used for determining series termination  
value.  
30  
:
Rev 1.0,November 21, 2006  
Page 11 of 13  
1...8910111213

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