Datasheet > W132-10B

W132-10B

更新时间： 2024-01-04 20:18:15

品牌	Logo	应用领域
其他 - ETC		时钟驱动器
页数	文件大小	规格书
13页	154K
描述
Ten Distributed-Output Clock Driver

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W132-10B 技术参数

生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	24
Reach Compliance Code：	unknown	风险等级：	5.75
Is Samacsys：	N	系列：	132
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G24
长度：	7.8 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	24	实输出次数：	10
最高工作温度：	70 °C	最低工作温度：
输出特性：	SERIES-RESISTOR	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	认证状态：	COMMERCIAL
Same Edge Skew-Max（tskwd）：	0.1 ns	座面最大高度：	1.1 mm
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	2.97 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
宽度：	4.4 mm	最小 fmax：	140 MHz
Base Number Matches：	1

W132-10B 数据手册

W134M/W134S

Table 8. State Transition Latency Specifications

Transition Latency

Transition

From

Symbol

Max.

Description

Power-down

Normal

t_POWERUP

3 ms

Time from PwrDnB to Clk/ClkB output settled

(excluding t_DISTLOCK).

Power-down

V_DDON

Clk Stop

Test

t_POWERUP

Time from PwrDnB until the internal PLL and

clock has turned ON and settled.

Time from PwrDnB to Clk/ClkB output settled

(excluding t_DISTLOCK).

Normal

Clk Stop

Time from V_DDis applied and settled until

Clk/ClkB output settled (excluding t_DISTLOCK).

V_DDON

Time from V_DDis applied and settled until

internal PLL and clock has turned ON and

settled.

V_DDON

Normal

Test

t_POWERUP

3 ms

1 ms

10 ns

Time from V_DDis applied and settled until

internal PLL and clock has turned ON and

settled.

Normal

t_MULT

Time from when Mult0 or Mult1 changed until

Clk/ClkB output resettled (excluding

t_DISTLOCK).

Clk Stop

Normal

t_CLKON

Time from StopB until Clk/ClkB provides

glitch-free clock edges.

t_CLKSETL

20 cycles Time from StopB to Clk/ClkB output settled to

within 50 ps of the phase before CLK/CLKB

was disabled.

Normal

Test

Clk Stop

Normal

t_CLKOFF

t_CTL

5 ns

Time from StopB Φ to Clk/ClkB output

disabled.

3 ms

Time from when S0 or S1 is changed until

CLK/CLKB output has resettled (excluding

t_DISTLOCK).

Normal

Test

t_CTL

3 ms

1 ms

Time from when S0 or S1 is changed until

CLK/CLKB output has resettled (excluding

t_DISTLOCK).

B,D

Normal or Clk Stop Power-down

t_POWERDN

Time from PwrDnB Φ to the device in Power-

down.

Figure 5 shows that the Clk Stop to Normal transition goes

through three phases. During t_CLKON, the clock output is not

specified and can have glitches. For t_CLKON< t < t_CLKSETL, the

clock output is enabled and must be glitch-free. For

t > t_CLKSETL, the clock output phase must be settled to within

50 ps of the phase before the clock output was disabled. At

this time, the clock output must also meet the voltage and tim-

ing specifications of Table 14. The outputs are in a high-imped-

ance state during the Clk Stop mode.

Document #: 38-07426 Rev. *A

Page 7 of 13

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与W132-10B相关器件

型号	品牌	描述	获取价格	数据表
W132-10BX	ROCHESTER	132 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, MO-15	获取价格
W132-10BXT	ROCHESTER	132 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, MO-15	获取价格
W132XGD	KINGBRIGHT	Single Color LED, Green, Diffused, T-1, 3mm,	获取价格
W132XGT	KINGBRIGHT	Single Color LED, Green, Transparent, T-1, 3mm,	获取价格
W132XIT	KINGBRIGHT	Single Color LED, High Efficiency Red, Red Transparent, T-1, 3mm,	获取价格
W132XNC	KINGBRIGHT	Single Color LED, Pure Orange, Water Clear, T-1, 3mm,	获取价格

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